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Searched refs:tiling_flags (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/radeon/
Dradeon_object.c594 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
599 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate()
615 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
654 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
676 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
684 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
685 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
686 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
687 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
688 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
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Dradeon_fb.c134 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
161 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
166 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
169 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
175 if (tiling_flags) { in radeonfb_create_pinned_object()
177 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
Dr200.c221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
Dradeon_object.h161 u32 tiling_flags, u32 pitch);
163 u32 *tiling_flags, u32 *pitch);
Dr300.c723 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
725 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
727 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
792 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
794 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
796 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
877 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
879 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
881 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
Dradeon_legacy_crtc.c386 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
466 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
Devergreen_cs.c93 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
95 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
97 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1180 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1181 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()
1185 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg()
1366 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1367 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1384 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
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Datombios_crtc.c1154 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1192 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1275 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1276 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1349 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1476 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1512 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1588 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1590 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1593 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
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Dr100.c1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1285 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1627 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1708 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3094 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3101 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3104 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3107 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
[all …]
Dr600_cs.c1042 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1141 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1144 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1472 u32 tiling_flags) in r600_check_texture_resource() argument
1494 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1496 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1965 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1967 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1983 reloc->tiling_flags); in r600_packet3_check()
Dradeon_gem.c511 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
532 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
Dradeon_vm.c146 list[0].tiling_flags = 0; in radeon_vm_get_bos()
158 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
Dradeon_display.c497 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local
543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target()
551 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
Dradeon.h356 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
470 uint32_t tiling_flags; member
502 u32 tiling_flags; member
1941 uint32_t tiling_flags, uint32_t pitch,
Dradeon_asic.h91 uint32_t tiling_flags, uint32_t pitch,
339 uint32_t tiling_flags, uint32_t pitch,
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_fb.c129 u32 tiling_flags = 0, domain; in amdgpufb_create_pinned_object() local
157 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object()
163 if (tiling_flags) { in amdgpufb_create_pinned_object()
165 tiling_flags); in amdgpufb_create_pinned_object()
Damdgpu_object.h93 u64 tiling_flags; member
277 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
278 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
Damdgpu_object.c1164 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument
1169 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1172 bo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags()
1184 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument
1188 if (tiling_flags) in amdgpu_bo_get_tiling_flags()
1189 *tiling_flags = bo->tiling_flags; in amdgpu_bo_get_tiling_flags()
Ddce_v6_0.c1817 uint64_t fb_location, tiling_flags; in dce_v6_0_crtc_do_set_base() local
1854 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v6_0_crtc_do_set_base()
1937 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1940 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v6_0_crtc_do_set_base()
1941 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v6_0_crtc_do_set_base()
1942 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v6_0_crtc_do_set_base()
1943 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1944 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
1952 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1956 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v6_0_crtc_do_set_base()
Ddce_v8_0.c1786 uint64_t fb_location, tiling_flags; in dce_v8_0_crtc_do_set_base() local
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v8_0_crtc_do_set_base()
1827 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v8_0_crtc_do_set_base()
1909 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1912 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v8_0_crtc_do_set_base()
1913 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v8_0_crtc_do_set_base()
1914 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v8_0_crtc_do_set_base()
1915 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1916 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
1925 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
Ddce_v10_0.c1857 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local
1895 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v10_0_crtc_do_set_base()
1898 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base()
1988 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
1991 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base()
1992 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base()
1993 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base()
1994 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
1995 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
2008 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c1899 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local
1937 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); in dce_v11_0_crtc_do_set_base()
1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base()
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base()
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base()
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base()
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
Damdgpu_display.c161 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local
216 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c3809 uint64_t *tiling_flags, bool *tmz_surface) in get_fb_info() argument
3815 *tiling_flags = 0; in get_fb_info()
3830 if (tiling_flags) in get_fb_info()
3831 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); in get_fb_info()
3841 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags) in get_dcc_address() argument
3843 uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B); in get_dcc_address()
3918 const uint64_t tiling_flags, in fill_plane_buffer_attributes() argument
3978 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_plane_buffer_attributes()
3981 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_buffer_attributes()
3982 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_plane_buffer_attributes()
[all …]
Damdgpu_dm.h411 uint64_t tiling_flags; member

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