| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_transform.c | 122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
166 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in dce60_setup_scaling_configuration()
303 dc_fixpt_from_int(data->taps.v_taps + 1)), in calculate_inits()
332 dc_fixpt_from_int(data->taps.v_taps + 1)), in dce60_calculate_inits()
439 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
449 data->taps.v_taps, in dce_transform_set_scaler()
454 data->taps.v_taps, in dce_transform_set_scaler()
525 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce60_transform_set_scaler()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp_dscl.c | 316 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
318 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
337 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
362 dpp, scl_data->taps.v_taps, in dpp1_dscl_set_scl_filter()
481 int vtaps = scl_data->taps.v_taps; in dpp1_dscl_find_lb_memory_config()
571 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, in dpp1_dscl_set_scaler_auto_scale()
731 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
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| D | dcn10_dpp.c | 166 if (in_taps->v_taps == 0) in dpp1_get_optimal_number_of_taps()
167 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps()
169 scl_data->taps.v_taps = in_taps->v_taps; in dpp1_get_optimal_number_of_taps()
186 scl_data->taps.v_taps = 1; in dpp1_get_optimal_number_of_taps()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_transform_v.c | 169 set_reg_field_value(value, data->taps.v_taps - 1, in setup_scaling_configuration()
178 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
562 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
574 data->taps.v_taps, in dce110_xfmv_set_scaler()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp.c | 412 if (in_taps->v_taps == 0) { in dpp3_get_optimal_number_of_taps()
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
416 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
418 scl_data->taps.v_taps = in_taps->v_taps; in dpp3_get_optimal_number_of_taps()
466 if (scl_data->taps.v_taps > max_taps_y) in dpp3_get_optimal_number_of_taps()
467 scl_data->taps.v_taps = max_taps_y; in dpp3_get_optimal_number_of_taps()
476 scl_data->taps.v_taps = 1; in dpp3_get_optimal_number_of_taps()
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| D | dcn30_resource.c | 1505 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; in dcn30_populate_dml_writeback_from_context()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 86 plane_state->scaling_quality.v_taps, in pre_surface_trace()
290 update->scaling_info->scaling_quality.v_taps, in update_surface_trace()
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| D | dc_resource.c | 1038 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19); in calculate_inits_and_adj_vp()
1051 orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps, in calculate_inits_and_adj_vp()
1069 orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps, in calculate_inits_and_adj_vp()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dce_calcs.c | 369 data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
370 data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
422 data->v_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
531 if (bw_mtn(data->vsr[i], data->v_taps[i])) { in calculate_bandwidth()
567 if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) { in calculate_bandwidth()
790 …data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i… in calculate_bandwidth()
810 …e[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data-… in calculate_bandwidth()
1244 …data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(da… in calculate_bandwidth()
1247 …ixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler… in calculate_bandwidth()
1302 …xed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixe… in calculate_bandwidth()
[all …]
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| D | calcs_logger.h | 431 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i])); in print_bw_calcs_data()
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| D | dcn_calcs.c | 404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
1031 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dwb_scl.c | 804 uint32_t v_taps_luma = num_taps.v_taps; in dwb_program_vert_scalar()
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| D | dcn20_resource.c | 2346 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_hw_types.h | 616 uint32_t v_taps; member
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | dce_calcs.h | 397 struct bw_fixed v_taps[maximum_number_of_surfaces]; member
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