| /drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 571 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
578 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
588 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
595 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
728 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
731 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
736 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
737 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
946 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
995 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.c | 898 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
910 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
943 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
954 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1458 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1692 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1695 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1935 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
2021 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2046 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| D | sumo_dpm.c | 824 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
840 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
858 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1414 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1417 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1804 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1827 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1835 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| D | rv770_dpm.c | 1438 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1445 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1455 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1462 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2153 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2156 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2161 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2162 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2440 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2484 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| D | rv6xx_dpm.c | 1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| D | radeon_uvd.c | 960 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
975 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
990 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | trinity_dpm.h | 69 u32 vclk; member
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| D | radeon_asic.h | 411 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
478 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
535 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
536 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
749 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
787 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | rv770.c | 49 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
51 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
58 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
65 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
71 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
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| D | ni_dpm.c | 3517 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3535 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3906 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ni_parse_pplib_non_clock_info()
3909 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in ni_parse_pplib_non_clock_info()
3912 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
4293 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4321 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
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| /drivers/video/fbdev/via/ |
| D | vt1636.c | 186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| D | chip.h | 141 u32 vclk; /*panel mode clock value */ member
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| /drivers/gpu/drm/exynos/ |
| D | exynos7_drm_decon.c | 50 struct clk *vclk; member
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
718 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
719 if (IS_ERR(ctx->vclk)) { in decon_probe()
721 ret = PTR_ERR(ctx->vclk); in decon_probe()
786 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
820 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
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| /drivers/media/platform/ |
| D | aspeed-video.c | 212 struct clk *vclk; member
524 clk_disable(video->vclk); in aspeed_video_off()
535 clk_enable(video->vclk); in aspeed_video_on()
1642 video->vclk = devm_clk_get(dev, "vclk"); in aspeed_video_init()
1643 if (IS_ERR(video->vclk)) { in aspeed_video_init()
1645 rc = PTR_ERR(video->vclk); in aspeed_video_init()
1649 rc = clk_prepare(video->vclk); in aspeed_video_init()
1674 clk_unprepare(video->vclk); in aspeed_video_init()
1727 clk_unprepare(video->vclk); in aspeed_video_probe()
1743 clk_unprepare(video->vclk); in aspeed_video_remove()
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| /drivers/video/fbdev/aty/ |
| D | aty128fb.c | 426 u32 vclk; member
1365 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1369 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1372 if (vclk > c.ppll_max) in aty128_var_to_pll()
1373 vclk = c.ppll_max; in aty128_var_to_pll()
1374 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1375 vclk = c.ppll_min/12; in aty128_var_to_pll()
1379 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1394 pll->vclk = vclk; in aty128_var_to_pll()
1398 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu8_hwmgr.c | 140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
597 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
599 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1415 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1722 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1756 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1757 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1893 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
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| D | hwmgr_ppt.h | 60 uint32_t vclk; /* UVD V-clock */ member
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| D | smu10_hwmgr.h | 97 uint32_t vclk; member
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| D | smu8_hwmgr.h | 114 uint32_t vclk; member
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| D | smu7_hwmgr.h | 68 uint32_t vclk; member
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 251 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
256 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | power_state.h | 183 unsigned long vclk; member
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| D | amdgpu_dpm.h | 60 u32 vclk; member
162 u32 vclk; member
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | si.c | 1598 unsigned vclk, unsigned dclk, in si_calc_upll_dividers() argument
1613 vco_min = max(max(vco_min, vclk), dclk); in si_calc_upll_dividers()
1627 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1639 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1659 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in si_set_uvd_clocks() argument
1672 if (!vclk || !dclk) { in si_set_uvd_clocks()
1677 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000, in si_set_uvd_clocks()
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| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | kv_dpm.c | 919 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
924 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
929 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
2276 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2652 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2655 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2887 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
3260 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in kv_check_state_equal()
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