1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
31 */
32
33 #ifndef _GVT_H_
34 #define _GVT_H_
35
36 #include "debug.h"
37 #include "hypercall.h"
38 #include "mmio.h"
39 #include "reg.h"
40 #include "interrupt.h"
41 #include "gtt.h"
42 #include "display.h"
43 #include "edid.h"
44 #include "execlist.h"
45 #include "scheduler.h"
46 #include "sched_policy.h"
47 #include "mmio_context.h"
48 #include "cmd_parser.h"
49 #include "fb_decoder.h"
50 #include "dmabuf.h"
51 #include "page_track.h"
52
53 #define GVT_MAX_VGPU 8
54
55 struct intel_gvt_host {
56 struct device *dev;
57 bool initialized;
58 int hypervisor_type;
59 struct intel_gvt_mpt *mpt;
60 };
61
62 extern struct intel_gvt_host intel_gvt_host;
63
64 /* Describe per-platform limitations. */
65 struct intel_gvt_device_info {
66 u32 max_support_vgpus;
67 u32 cfg_space_size;
68 u32 mmio_size;
69 u32 mmio_bar;
70 unsigned long msi_cap_offset;
71 u32 gtt_start_offset;
72 u32 gtt_entry_size;
73 u32 gtt_entry_size_shift;
74 int gmadr_bytes_in_cmd;
75 u32 max_surface_size;
76 };
77
78 /* GM resources owned by a vGPU */
79 struct intel_vgpu_gm {
80 u64 aperture_sz;
81 u64 hidden_sz;
82 struct drm_mm_node low_gm_node;
83 struct drm_mm_node high_gm_node;
84 };
85
86 #define INTEL_GVT_MAX_NUM_FENCES 32
87
88 /* Fences owned by a vGPU */
89 struct intel_vgpu_fence {
90 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
91 u32 base;
92 u32 size;
93 };
94
95 struct intel_vgpu_mmio {
96 void *vreg;
97 };
98
99 #define INTEL_GVT_MAX_BAR_NUM 4
100
101 struct intel_vgpu_pci_bar {
102 u64 size;
103 bool tracked;
104 };
105
106 struct intel_vgpu_cfg_space {
107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
109 u32 pmcsr_off;
110 };
111
112 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
113
114 struct intel_vgpu_irq {
115 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
116 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
117 INTEL_GVT_EVENT_MAX);
118 };
119
120 struct intel_vgpu_opregion {
121 bool mapped;
122 void *va;
123 u32 gfn[INTEL_GVT_OPREGION_PAGES];
124 };
125
126 #define vgpu_opregion(vgpu) (&(vgpu->opregion))
127
128 struct intel_vgpu_display {
129 struct intel_vgpu_i2c_edid i2c_edid;
130 struct intel_vgpu_port ports[I915_MAX_PORTS];
131 struct intel_vgpu_sbi sbi;
132 };
133
134 struct vgpu_sched_ctl {
135 int weight;
136 };
137
138 enum {
139 INTEL_VGPU_EXECLIST_SUBMISSION = 1,
140 INTEL_VGPU_GUC_SUBMISSION,
141 };
142
143 struct intel_vgpu_submission_ops {
144 const char *name;
145 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
148 };
149
150 struct intel_vgpu_submission {
151 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
152 struct list_head workload_q_head[I915_NUM_ENGINES];
153 struct intel_context *shadow[I915_NUM_ENGINES];
154 struct kmem_cache *workloads;
155 atomic_t running_workload_num;
156 union {
157 u64 i915_context_pml4;
158 u64 i915_context_pdps[GEN8_3LVL_PDPES];
159 };
160 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
161 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
162 void *ring_scan_buffer[I915_NUM_ENGINES];
163 int ring_scan_buffer_size[I915_NUM_ENGINES];
164 const struct intel_vgpu_submission_ops *ops;
165 int virtual_submission_interface;
166 bool active;
167 struct {
168 u32 lrca;
169 bool valid;
170 u64 ring_context_gpa;
171 } last_ctx[I915_NUM_ENGINES];
172 };
173
174 struct intel_vgpu {
175 struct intel_gvt *gvt;
176 struct mutex vgpu_lock;
177 int id;
178 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
179 bool active;
180 bool pv_notified;
181 bool failsafe;
182 unsigned int resetting_eng;
183
184 /* Both sched_data and sched_ctl can be seen a part of the global gvt
185 * scheduler structure. So below 2 vgpu data are protected
186 * by sched_lock, not vgpu_lock.
187 */
188 void *sched_data;
189 struct vgpu_sched_ctl sched_ctl;
190
191 struct intel_vgpu_fence fence;
192 struct intel_vgpu_gm gm;
193 struct intel_vgpu_cfg_space cfg_space;
194 struct intel_vgpu_mmio mmio;
195 struct intel_vgpu_irq irq;
196 struct intel_vgpu_gtt gtt;
197 struct intel_vgpu_opregion opregion;
198 struct intel_vgpu_display display;
199 struct intel_vgpu_submission submission;
200 struct radix_tree_root page_track_tree;
201 u32 hws_pga[I915_NUM_ENGINES];
202 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
203 bool d3_entered;
204
205 struct dentry *debugfs;
206
207 /* Hypervisor-specific device state. */
208 void *vdev;
209
210 struct list_head dmabuf_obj_list_head;
211 struct mutex dmabuf_lock;
212 struct idr object_idr;
213
214 u32 scan_nonprivbb;
215 };
216
intel_vgpu_vdev(struct intel_vgpu * vgpu)217 static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu)
218 {
219 return vgpu->vdev;
220 }
221
222 /* validating GM healthy status*/
223 #define vgpu_is_vm_unhealthy(ret_val) \
224 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
225
226 struct intel_gvt_gm {
227 unsigned long vgpu_allocated_low_gm_size;
228 unsigned long vgpu_allocated_high_gm_size;
229 };
230
231 struct intel_gvt_fence {
232 unsigned long vgpu_allocated_fence_num;
233 };
234
235 /* Special MMIO blocks. */
236 struct gvt_mmio_block {
237 unsigned int device;
238 i915_reg_t offset;
239 unsigned int size;
240 gvt_mmio_func read;
241 gvt_mmio_func write;
242 };
243
244 #define INTEL_GVT_MMIO_HASH_BITS 11
245
246 struct intel_gvt_mmio {
247 u8 *mmio_attribute;
248 /* Register contains RO bits */
249 #define F_RO (1 << 0)
250 /* Register contains graphics address */
251 #define F_GMADR (1 << 1)
252 /* Mode mask registers with high 16 bits as the mask bits */
253 #define F_MODE_MASK (1 << 2)
254 /* This reg can be accessed by GPU commands */
255 #define F_CMD_ACCESS (1 << 3)
256 /* This reg has been accessed by a VM */
257 #define F_ACCESSED (1 << 4)
258 /* This reg requires save & restore during host PM suspend/resume */
259 #define F_PM_SAVE (1 << 5)
260 /* This reg could be accessed by unaligned address */
261 #define F_UNALIGN (1 << 6)
262 /* This reg is in GVT's mmio save-restor list and in hardware
263 * logical context image
264 */
265 #define F_SR_IN_CTX (1 << 7)
266
267 struct gvt_mmio_block *mmio_block;
268 unsigned int num_mmio_block;
269
270 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
271 unsigned long num_tracked_mmio;
272 };
273
274 struct intel_gvt_firmware {
275 void *cfg_space;
276 void *mmio;
277 bool firmware_loaded;
278 };
279
280 #define NR_MAX_INTEL_VGPU_TYPES 20
281 struct intel_vgpu_type {
282 char name[16];
283 unsigned int avail_instance;
284 unsigned int low_gm_size;
285 unsigned int high_gm_size;
286 unsigned int fence;
287 unsigned int weight;
288 enum intel_vgpu_edid resolution;
289 };
290
291 struct intel_gvt {
292 /* GVT scope lock, protect GVT itself, and all resource currently
293 * not yet protected by special locks(vgpu and scheduler lock).
294 */
295 struct mutex lock;
296 /* scheduler scope lock, protect gvt and vgpu schedule related data */
297 struct mutex sched_lock;
298
299 struct intel_gt *gt;
300 struct idr vgpu_idr; /* vGPU IDR pool */
301
302 struct intel_gvt_device_info device_info;
303 struct intel_gvt_gm gm;
304 struct intel_gvt_fence fence;
305 struct intel_gvt_mmio mmio;
306 struct intel_gvt_firmware firmware;
307 struct intel_gvt_irq irq;
308 struct intel_gvt_gtt gtt;
309 struct intel_gvt_workload_scheduler scheduler;
310 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
311 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
312 struct intel_vgpu_type *types;
313 unsigned int num_types;
314 struct intel_vgpu *idle_vgpu;
315
316 struct task_struct *service_thread;
317 wait_queue_head_t service_thread_wq;
318
319 /* service_request is always used in bit operation, we should always
320 * use it with atomic bit ops so that no need to use gvt big lock.
321 */
322 unsigned long service_request;
323
324 struct {
325 struct engine_mmio *mmio;
326 int ctx_mmio_count[I915_NUM_ENGINES];
327 u32 *tlb_mmio_offset_list;
328 u32 tlb_mmio_offset_list_cnt;
329 u32 *mocs_mmio_offset_list;
330 u32 mocs_mmio_offset_list_cnt;
331 } engine_mmio_list;
332
333 struct dentry *debugfs_root;
334 };
335
to_gvt(struct drm_i915_private * i915)336 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
337 {
338 return i915->gvt;
339 }
340
341 enum {
342 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
343
344 /* Scheduling trigger by timer */
345 INTEL_GVT_REQUEST_SCHED = 1,
346
347 /* Scheduling trigger by event */
348 INTEL_GVT_REQUEST_EVENT_SCHED = 2,
349 };
350
intel_gvt_request_service(struct intel_gvt * gvt,int service)351 static inline void intel_gvt_request_service(struct intel_gvt *gvt,
352 int service)
353 {
354 set_bit(service, (void *)&gvt->service_request);
355 wake_up(&gvt->service_thread_wq);
356 }
357
358 void intel_gvt_free_firmware(struct intel_gvt *gvt);
359 int intel_gvt_load_firmware(struct intel_gvt *gvt);
360
361 /* Aperture/GM space definitions for GVT device */
362 #define MB_TO_BYTES(mb) ((mb) << 20ULL)
363 #define BYTES_TO_MB(b) ((b) >> 20ULL)
364
365 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
366 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
367 #define HOST_FENCE 4
368
369 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
370
371 /* Aperture/GM space definitions for GVT device */
372 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
373 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
374
375 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
376 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
377 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
378
379 #define gvt_aperture_gmadr_base(gvt) (0)
380 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
381 + gvt_aperture_sz(gvt) - 1)
382
383 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
384 + gvt_aperture_sz(gvt))
385 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
386 + gvt_hidden_sz(gvt) - 1)
387
388 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
389
390 /* Aperture/GM space definitions for vGPU */
391 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
392 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
393 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
394 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
395
396 #define vgpu_aperture_pa_base(vgpu) \
397 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
398
399 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
400
401 #define vgpu_aperture_pa_end(vgpu) \
402 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
403
404 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
405 #define vgpu_aperture_gmadr_end(vgpu) \
406 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
407
408 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
409 #define vgpu_hidden_gmadr_end(vgpu) \
410 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
411
412 #define vgpu_fence_base(vgpu) (vgpu->fence.base)
413 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
414
415 struct intel_vgpu_creation_params {
416 __u64 handle;
417 __u64 low_gm_sz; /* in MB */
418 __u64 high_gm_sz; /* in MB */
419 __u64 fence_sz;
420 __u64 resolution;
421 __s32 primary;
422 __u64 vgpu_id;
423
424 __u32 weight;
425 };
426
427 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
428 struct intel_vgpu_creation_params *param);
429 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
430 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
431 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
432 u32 fence, u64 value);
433
434 /* Macros for easily accessing vGPU virtual/shadow register.
435 Explicitly seperate use for typed MMIO reg or real offset.*/
436 #define vgpu_vreg_t(vgpu, reg) \
437 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
438 #define vgpu_vreg(vgpu, offset) \
439 (*(u32 *)(vgpu->mmio.vreg + (offset)))
440 #define vgpu_vreg64_t(vgpu, reg) \
441 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
442 #define vgpu_vreg64(vgpu, offset) \
443 (*(u64 *)(vgpu->mmio.vreg + (offset)))
444
445 #define for_each_active_vgpu(gvt, vgpu, id) \
446 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
447 for_each_if(vgpu->active)
448
intel_vgpu_write_pci_bar(struct intel_vgpu * vgpu,u32 offset,u32 val,bool low)449 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
450 u32 offset, u32 val, bool low)
451 {
452 u32 *pval;
453
454 /* BAR offset should be 32 bits algiend */
455 offset = rounddown(offset, 4);
456 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
457
458 if (low) {
459 /*
460 * only update bit 31 - bit 4,
461 * leave the bit 3 - bit 0 unchanged.
462 */
463 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
464 } else {
465 *pval = val;
466 }
467 }
468
469 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
470 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
471
472 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
473 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
474 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
475 struct intel_vgpu_type *type);
476 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
477 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
478 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
479 intel_engine_mask_t engine_mask);
480 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
481 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
482 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
483
484 /* validating GM functions */
485 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \
486 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
487 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
488
489 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \
490 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
491 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
492
493 #define vgpu_gmadr_is_valid(vgpu, gmadr) \
494 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
495 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
496
497 #define gvt_gmadr_is_aperture(gvt, gmadr) \
498 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
499 (gmadr <= gvt_aperture_gmadr_end(gvt)))
500
501 #define gvt_gmadr_is_hidden(gvt, gmadr) \
502 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
503 (gmadr <= gvt_hidden_gmadr_end(gvt)))
504
505 #define gvt_gmadr_is_valid(gvt, gmadr) \
506 (gvt_gmadr_is_aperture(gvt, gmadr) || \
507 gvt_gmadr_is_hidden(gvt, gmadr))
508
509 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
510 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
511 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
512 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
513 unsigned long *h_index);
514 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
515 unsigned long *g_index);
516
517 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
518 bool primary);
519 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
520
521 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
522 void *p_data, unsigned int bytes);
523
524 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
525 void *p_data, unsigned int bytes);
526
527 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
528
intel_vgpu_get_bar_gpa(struct intel_vgpu * vgpu,int bar)529 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
530 {
531 /* We are 64bit bar. */
532 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
533 PCI_BASE_ADDRESS_MEM_MASK;
534 }
535
536 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
537 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
538 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
539
540 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
541 void populate_pvinfo_page(struct intel_vgpu *vgpu);
542
543 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
544 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
545
546 struct intel_gvt_ops {
547 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *,
548 unsigned int);
549 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *,
550 unsigned int);
551 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *,
552 unsigned int);
553 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *,
554 unsigned int);
555 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *,
556 struct intel_vgpu_type *);
557 void (*vgpu_destroy)(struct intel_vgpu *vgpu);
558 void (*vgpu_release)(struct intel_vgpu *vgpu);
559 void (*vgpu_reset)(struct intel_vgpu *);
560 void (*vgpu_activate)(struct intel_vgpu *);
561 void (*vgpu_deactivate)(struct intel_vgpu *);
562 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt,
563 const char *name);
564 bool (*get_gvt_attrs)(struct attribute_group ***intel_vgpu_type_groups);
565 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
566 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int);
567 int (*write_protect_handler)(struct intel_vgpu *, u64, void *,
568 unsigned int);
569 void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected);
570 };
571
572
573 enum {
574 GVT_FAILSAFE_UNSUPPORTED_GUEST,
575 GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
576 GVT_FAILSAFE_GUEST_ERR,
577 };
578
mmio_hw_access_pre(struct intel_gt * gt)579 static inline void mmio_hw_access_pre(struct intel_gt *gt)
580 {
581 intel_runtime_pm_get(gt->uncore->rpm);
582 }
583
mmio_hw_access_post(struct intel_gt * gt)584 static inline void mmio_hw_access_post(struct intel_gt *gt)
585 {
586 intel_runtime_pm_put_unchecked(gt->uncore->rpm);
587 }
588
589 /**
590 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
591 * @gvt: a GVT device
592 * @offset: register offset
593 *
594 */
intel_gvt_mmio_set_accessed(struct intel_gvt * gvt,unsigned int offset)595 static inline void intel_gvt_mmio_set_accessed(
596 struct intel_gvt *gvt, unsigned int offset)
597 {
598 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
599 }
600
601 /**
602 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command
603 * @gvt: a GVT device
604 * @offset: register offset
605 *
606 * Returns:
607 * True if an MMIO is able to be accessed by GPU commands
608 */
intel_gvt_mmio_is_cmd_accessible(struct intel_gvt * gvt,unsigned int offset)609 static inline bool intel_gvt_mmio_is_cmd_accessible(
610 struct intel_gvt *gvt, unsigned int offset)
611 {
612 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
613 }
614
615 /**
616 * intel_gvt_mmio_set_cmd_accessible -
617 * mark a MMIO could be accessible by command
618 * @gvt: a GVT device
619 * @offset: register offset
620 *
621 */
intel_gvt_mmio_set_cmd_accessible(struct intel_gvt * gvt,unsigned int offset)622 static inline void intel_gvt_mmio_set_cmd_accessible(
623 struct intel_gvt *gvt, unsigned int offset)
624 {
625 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;
626 }
627
628 /**
629 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
630 * @gvt: a GVT device
631 * @offset: register offset
632 *
633 */
intel_gvt_mmio_is_unalign(struct intel_gvt * gvt,unsigned int offset)634 static inline bool intel_gvt_mmio_is_unalign(
635 struct intel_gvt *gvt, unsigned int offset)
636 {
637 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
638 }
639
640 /**
641 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
642 * @gvt: a GVT device
643 * @offset: register offset
644 *
645 * Returns:
646 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
647 *
648 */
intel_gvt_mmio_has_mode_mask(struct intel_gvt * gvt,unsigned int offset)649 static inline bool intel_gvt_mmio_has_mode_mask(
650 struct intel_gvt *gvt, unsigned int offset)
651 {
652 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
653 }
654
655 /**
656 * intel_gvt_mmio_is_sr_in_ctx -
657 * check if an MMIO has F_SR_IN_CTX mask
658 * @gvt: a GVT device
659 * @offset: register offset
660 *
661 * Returns:
662 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't.
663 *
664 */
intel_gvt_mmio_is_sr_in_ctx(struct intel_gvt * gvt,unsigned int offset)665 static inline bool intel_gvt_mmio_is_sr_in_ctx(
666 struct intel_gvt *gvt, unsigned int offset)
667 {
668 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
669 }
670
671 /**
672 * intel_gvt_mmio_set_sr_in_ctx -
673 * mask an MMIO in GVT's mmio save-restore list and also
674 * in hardware logical context image
675 * @gvt: a GVT device
676 * @offset: register offset
677 *
678 */
intel_gvt_mmio_set_sr_in_ctx(struct intel_gvt * gvt,unsigned int offset)679 static inline void intel_gvt_mmio_set_sr_in_ctx(
680 struct intel_gvt *gvt, unsigned int offset)
681 {
682 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
683 }
684
685 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
686 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
687 void intel_gvt_debugfs_init(struct intel_gvt *gvt);
688 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
689
690 int intel_gvt_pm_resume(struct intel_gvt *gvt);
691
692 #include "trace.h"
693 #include "mpt.h"
694
695 #endif
696