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Searched refs:vgpu_vreg (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/gvt/
Dedid.c141 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in gmbus0_mmio_write()
143 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK; in gmbus0_mmio_write()
182 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) { in gmbus1_mmio_write()
184 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT; in gmbus1_mmio_write()
237 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset)) in gmbus1_mmio_write()
271 vgpu_vreg(vgpu, offset) = wvalue; in gmbus1_mmio_write()
299 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read()
310 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count); in gmbus3_mmio_read()
311 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read()
332 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in gmbus3_mmio_read()
[all …]
Dinterrupt.c182 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_imr_handler()
183 (vgpu_vreg(vgpu, reg) ^ imr)); in intel_vgpu_reg_imr_handler()
185 vgpu_vreg(vgpu, reg) = imr; in intel_vgpu_reg_imr_handler()
211 u32 virtual_ier = vgpu_vreg(vgpu, reg); in intel_vgpu_reg_master_irq_handler()
223 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; in intel_vgpu_reg_master_irq_handler()
224 vgpu_vreg(vgpu, reg) |= ier; in intel_vgpu_reg_master_irq_handler()
253 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_ier_handler()
254 (vgpu_vreg(vgpu, reg) ^ ier)); in intel_vgpu_reg_ier_handler()
256 vgpu_vreg(vgpu, reg) = ier; in intel_vgpu_reg_ier_handler()
291 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler()
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Dhandlers.c77 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in read_vreg()
83 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in write_vreg()
285 old = vgpu_vreg(vgpu, offset); in mul_force_wake_write()
308 vgpu_vreg(vgpu, offset) = new; in mul_force_wake_write()
309 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write()
320 data = vgpu_vreg(vgpu, offset); in gdrst_mmio_write()
357 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
379 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { in pch_pp_control_mmio_write()
397 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) in transconf_mmio_write()
398 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; in transconf_mmio_write()
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Dexeclist.c98 status.ldw = vgpu_vreg(vgpu, status_reg); in emulate_execlist_status()
99 status.udw = vgpu_vreg(vgpu, status_reg + 4); in emulate_execlist_status()
117 vgpu_vreg(vgpu, status_reg) = status.ldw; in emulate_execlist_status()
118 vgpu_vreg(vgpu, status_reg + 4) = status.udw; in emulate_execlist_status()
139 ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg); in emulate_csb_update()
152 vgpu_vreg(vgpu, offset) = status->ldw; in emulate_csb_update()
153 vgpu_vreg(vgpu, offset + 4) = status->udw; in emulate_csb_update()
156 vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw; in emulate_csb_update()
262 status.ldw = vgpu_vreg(vgpu, status_reg); in get_next_execlist_slot()
263 status.udw = vgpu_vreg(vgpu, status_reg + 4); in get_next_execlist_slot()
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Ddebugfs.c66 vreg = vgpu_vreg(param->vgpu, offset); in mmio_diff_handler()
Ddisplay.c40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); in get_edp_pipe()
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) in edp_pipe_is_enabled()
Dscheduler.c256 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
260 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
264 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
Dgvt.h438 #define vgpu_vreg(vgpu, offset) \ macro
Dcmd_parser.c881 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1); in mocs_cmd_reg_handler()
991 vgpu_vreg(vgpu, offset) = data; in cmd_reg_handler()