| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 62 int vready_offset, in optc1_program_global_sync() argument
69 optc1->vready_offset = vready_offset; in optc1_program_global_sync()
87 VREADY_OFFSET, optc1->vready_offset); in optc1_program_global_sync()
142 int vready_offset, in optc1_program_timing() argument
162 optc1->vready_offset = vready_offset; in optc1_program_timing()
270 vready_offset, in optc1_program_timing()
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| D | dcn10_optc.h | 579 int vready_offset; member
620 int vready_offset,
640 int vready_offset,
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| D | dcn10_hubp.c | 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width in hubp1_vready_workaround()
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| D | dcn10_hw_sequencer.c | 816 pipe_ctx->pipe_dlg_param.vready_offset, in dcn10_enable_stream_timing()
2733 pipe_ctx->pipe_dlg_param.vready_offset, in dcn10_program_all_pipe_in_tree()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | timing_generator.h | 154 int vready_offset,
234 int vready_offset,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 866 unsigned int vready_offset; in dml20_rq_dlg_get_dlg_params() local
1014 vready_offset = dst->vready_offset; in dml20_rq_dlg_get_dlg_params()
1039 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20_rq_dlg_get_dlg_params()
1046 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20v2.c | 866 unsigned int vready_offset; in dml20v2_rq_dlg_get_dlg_params() local
1015 vready_offset = dst->vready_offset; in dml20v2_rq_dlg_get_dlg_params()
1040 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20v2_rq_dlg_get_dlg_params()
1047 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml20v2_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_timing_generator.c | 110 int vready_offset, in program_timing() argument
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator.h | 260 int vready_offset,
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| D | dce110_timing_generator_v.c | 438 int vready_offset, in dce110_timing_generator_v_program_timing() argument
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| D | dce110_timing_generator.c | 1960 int vready_offset, in dce110_tg_program_timing() argument
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1063 unsigned int vready_offset; in dml1_rq_dlg_get_dlg_params() local
1245 vready_offset = e2e_pipe_param.pipe.dest.vready_offset; in dml1_rq_dlg_get_dlg_params()
1314 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal; in dml1_rq_dlg_get_dlg_params()
1341 DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset); in dml1_rq_dlg_get_dlg_params()
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| D | display_mode_structs.h | 346 unsigned int vready_offset; member
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| D | display_mode_lib.c | 203 dml_print("DML PARAMS: vready_offset = %d\n", pipe_dest->vready_offset); in dml_log_pipe_params()
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| D | display_mode_vba.h | 104 dml_get_pipe_attr_decl(vready_offset);
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| D | display_mode_vba.c | 160 dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 912 unsigned int vready_offset; in dml_rq_dlg_get_dlg_params() local
1054 vready_offset = dst->vready_offset; in dml_rq_dlg_get_dlg_params()
1079 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
1086 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_timing_generator.c | 110 int vready_offset, in program_timing() argument
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 1066 unsigned int vready_offset = 0; in dml_rq_dlg_get_dlg_params() local
1203 vready_offset = dst->vready_offset; in dml_rq_dlg_get_dlg_params()
1228 - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
1235 - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 700 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
1275 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1582 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_program_pipe()
1836 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_update_bandwidth()
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| D | dcn20_hubp.c | 185 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width in hubp2_vready_at_or_After_vsync()
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| D | dcn20_resource.c | 3101 …pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,…
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_timing_generator.c | 739 int vready_offset, in dce120_tg_program_timing() argument
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 1229 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
1270 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
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