Home
last modified time | relevance | path

Searched refs:writeq (Results 1 – 25 of 148) sorted by relevance

123456

/drivers/infiniband/hw/hfi1/
Dpio_copy.c79 writeq(pbc, dest); in pio_copy()
92 writeq(*(u64 *)from, dest); in pio_copy()
108 writeq(*(u64 *)from, dest); in pio_copy()
127 writeq(*(u64 *)from, dest); in pio_copy()
138 writeq(*(u64 *)from, dest); in pio_copy()
151 writeq(val.val64, dest); in pio_copy()
159 writeq(0, dest); in pio_copy()
265 writeq(temp, dest); in merge_write8()
274 writeq(carry.val64, dest); in carry8_write8()
286 writeq(pbuf->carry.val64, dest); in carry_write8()
[all …]
/drivers/net/ethernet/neterion/
Ds2io.c1135 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1160 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1165 writeq(val64, &bar0->tti_command_mem); in init_tti()
1210 writeq(val64, &bar0->sw_reset); in init_nic()
1217 writeq(val64, &bar0->sw_reset); in init_nic()
1239 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1241 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1251 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1272 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1273 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
[all …]
/drivers/fpga/
Ddfl-fme-error.c73 writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK); in pcie0_errors_store()
77 writeq(v, base + PCIE0_ERROR); in pcie0_errors_store()
81 writeq(0ULL, base + PCIE0_ERROR_MASK); in pcie0_errors_store()
118 writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK); in pcie1_errors_store()
122 writeq(v, base + PCIE1_ERROR); in pcie1_errors_store()
126 writeq(0ULL, base + PCIE1_ERROR_MASK); in pcie1_errors_store()
194 writeq(v, base + RAS_ERROR_INJECT); in inject_errors_store()
232 writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK); in fme_errors_store()
236 writeq(v, base + FME_ERROR); in fme_errors_store()
241 writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR, in fme_errors_store()
[all …]
Ddfl-fme-mgr.c102 writeq(pr_error, fme_pr + FME_PR_ERR); in fme_mgr_pr_error_handle()
125 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
136 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
160 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_init()
178 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write()
211 writeq(pr_data, fme_pr + FME_PR_DATA); in fme_mgr_write()
230 writeq(pr_ctrl, fme_pr + FME_PR_CTRL); in fme_mgr_write_complete()
Ddfl-afu-error.c37 writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK); in __afu_port_err_mask()
94 writeq(v, base_err + PORT_ERROR); in afu_port_err_clear()
97 writeq(v, base_err + PORT_FIRST_ERROR); in afu_port_err_clear()
/drivers/gpio/
Dgpio-mlxbf.c114 writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD); in mlxbf_gpio_resume()
115 writeq(gs->csave_regs.pad_control[0], in mlxbf_gpio_resume()
117 writeq(gs->csave_regs.pad_control[1], in mlxbf_gpio_resume()
119 writeq(gs->csave_regs.pad_control[2], in mlxbf_gpio_resume()
121 writeq(gs->csave_regs.pad_control[3], in mlxbf_gpio_resume()
123 writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I); in mlxbf_gpio_resume()
124 writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O); in mlxbf_gpio_resume()
Dgpio-thunderx.c114 writeq(txgpio->line_entries[line].fil_bits, in thunderx_gpio_dir_in()
130 writeq(BIT_ULL(bank_bit), reg); in thunderx_gpio_set()
152 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_dir_out()
240 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); in thunderx_gpio_set_config()
284 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
285 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); in thunderx_gpio_set_multiple()
294 writeq(GPIO_INTR_INTR, in thunderx_gpio_irq_ack()
303 writeq(GPIO_INTR_ENA_W1C, in thunderx_gpio_irq_mask()
312 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, in thunderx_gpio_irq_mask_ack()
321 writeq(GPIO_INTR_ENA_W1S, in thunderx_gpio_irq_unmask()
[all …]
/drivers/mmc/host/
Dcavium.c212 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
215 writeq(emm_switch, host->base + MIO_EMM_SWITCH(host)); in do_switch()
247 writeq(timeout, slot->host->base + MIO_EMM_WDOG(slot->host)); in set_wdog()
267 writeq(wdog, slot->host->base + MIO_EMM_WDOG(host)); in cvm_mmc_reset_bus()
286 writeq(slot->cached_rca, host->base + MIO_EMM_RCA(host)); in cvm_mmc_switch_to()
293 writeq(emm_sample, host->base + MIO_EMM_SAMPLE(host)); in cvm_mmc_switch_to()
307 writeq((0x10000 | (dbuf << 6)), host->base + MIO_EMM_BUF_IDX(host)); in do_read()
396 writeq(BIT_ULL(16), host->dma_base + MIO_EMM_DMA_FIFO_CFG(host)); in finish_dma_sg()
432 writeq(emm_dma, host->base + MIO_EMM_DMA(host)); in cleanup_dma()
450 writeq(emm_int, host->base + MIO_EMM_INT(host)); in cvm_mmc_interrupt()
[all …]
Dcavium-thunderx.c32 writeq(val, host->base + MIO_EMM_INT(host)); in thunder_mmc_int_enable()
33 writeq(val, host->base + MIO_EMM_INT_EN_SET(host)); in thunder_mmc_int_enable()
122 writeq(127, host->base + MIO_EMM_INT_EN(host)); in thunder_mmc_probe()
123 writeq(3, host->base + MIO_EMM_DMA_INT_ENA_W1C(host)); in thunder_mmc_probe()
125 writeq(BIT_ULL(16), host->base + MIO_EMM_DMA_FIFO_CFG(host)); in thunder_mmc_probe()
182 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in thunder_mmc_remove()
Dcavium-octeon.c94 writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL); in octeon_mmc_acquire_bus()
110 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_int_enable()
112 writeq(val, host->base + MIO_EMM_INT_EN(host)); in octeon_mmc_int_enable()
233 writeq(val, host->base + MIO_EMM_INT(host)); in octeon_mmc_probe()
309 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host)); in octeon_mmc_remove()
/drivers/net/ethernet/cavium/liquidio/
Docteon_mailbox.c80 writeq(OCTEON_PFVFERR, in octeon_mbox_read()
115 writeq(OCTEON_PFVFACK, mbox->mbox_read_reg); in octeon_mbox_read()
172 writeq(mbox_cmd->msg.u64, mbox->mbox_write_reg); in octeon_mbox_write()
184 writeq(mbox_cmd->data[i], mbox->mbox_write_reg); in octeon_mbox_write()
193 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_write()
306 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
316 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
325 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
341 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_process_message()
371 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in octeon_mbox_cancel()
Dcn23xx_pf_device.c466 writeq((readq(inst_cnt_reg) & in cn23xx_pf_setup_global_input_regs()
543 writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK); in cn23xx_pf_setup_global_output_regs()
551 writeq(readq((u8 *)oct->mmio[0].hw_addr + in cn23xx_pf_setup_global_output_regs()
557 writeq(0xffffffffffffffffULL, in cn23xx_pf_setup_global_output_regs()
560 writeq(0xffffffffffffffffULL, in cn23xx_pf_setup_global_output_regs()
616 writeq((pkt_in_done | CN23XX_INTR_CINT_ENB), in cn23xx_setup_iq_regs()
622 writeq(pkt_in_done, iq->inst_cnt_reg); in cn23xx_setup_iq_regs()
689 writeq(mbox_int_val, mbox->mbox_int_reg); in cn23xx_pf_mbox_thread()
755 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); in cn23xx_setup_pf_mbox()
996 writeq(BIT_ULL(q_no), in cn23xx_handle_pf_mbox_intr()
[all …]
/drivers/net/ethernet/neterion/vxge/
Dvxge-traffic.c50 writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg); in vxge_hw_vpath_intr_enable()
106 writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW| in vxge_hw_vpath_intr_enable()
178 writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask); in vxge_hw_vpath_intr_disable()
234 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); in vxge_hw_vpath_tti_ci_set()
244 writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); in vxge_hw_vpath_dynamic_rti_ci_set()
257 writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); in vxge_hw_vpath_dynamic_tti_rtimer_set()
273 writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); in vxge_hw_vpath_dynamic_rti_rtimer_set()
381 writeq(val64, &hldev->common_reg->tim_int_status0); in vxge_hw_device_intr_enable()
383 writeq(~val64, &hldev->common_reg->tim_int_mask0); in vxge_hw_device_intr_enable()
418 writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0); in vxge_hw_device_intr_disable()
[all …]
Dvxge-config.c40 writeq(val64, &vp_reg->rxmac_vcfg0); in vxge_hw_vpath_set_zero_rx_frm_len()
172 writeq(*data0, &vp_reg->rts_access_steer_data0); in vxge_hw_vpath_fw_api()
173 writeq(*data1, &vp_reg->rts_access_steer_data1); in vxge_hw_vpath_fw_api()
529 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
531 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
533 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
535 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
540 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
542 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, in __vxge_hw_legacy_swapper_set()
547 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, in __vxge_hw_legacy_swapper_set()
[all …]
/drivers/crypto/marvell/octeontx/
Dotx_cptpf_mbox.c78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
120 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_qlen_for_vf()
132 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(vf)); in otx_cpt_cfg_vq_priority()
162 writeq(pf_qx_ctl.u, cpt->reg_base + OTX_CPT_PF_QX_CTL(q)); in otx_cpt_bind_vq_to_grp()
Dotx_cptvf_main.c354 writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); in cptvf_write_vq_ctl()
363 writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); in otx_cptvf_write_vq_doorbell()
372 writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); in cptvf_write_vq_inprog()
381 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_numwait()
398 writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); in cptvf_write_vq_done_timewait()
417 writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); in cptvf_enable_swerr_interrupts()
427 writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); in cptvf_enable_mbox_interrupts()
437 writeq(vqx_done_ena.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0)); in cptvf_enable_done_interrupts()
447 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_dovf_intr()
457 writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); in cptvf_clear_irde_intr()
[all …]
/drivers/spi/
Dspi-cavium.c66 writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p)); in octeon_spi_do_transfer()
78 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
85 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
102 writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i)); in octeon_spi_do_transfer()
113 writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p)); in octeon_spi_do_transfer()
/drivers/edac/
Dthunderx_edac.c281 writeq(val, pdata->regs + _reg); \
315 writeq(val, lmc->regs + LMC_INT_W1S); in thunderx_lmc_inject_int_write()
351 writeq(lmc->mask0, lmc->regs + LMC_CHAR_MASK0); in inject_ecc_fn()
352 writeq(lmc->mask2, lmc->regs + LMC_CHAR_MASK2); in inject_ecc_fn()
353 writeq(lmc->parity_test, lmc->regs + LMC_ECC_PARITY_TEST); in inject_ecc_fn()
553 writeq(0, lmc->regs + LMC_CHAR_MASK0); in thunderx_lmc_err_isr()
554 writeq(0, lmc->regs + LMC_CHAR_MASK2); in thunderx_lmc_err_isr()
555 writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST); in thunderx_lmc_err_isr()
568 writeq(ctx->reg_int, lmc->regs + LMC_INT); in thunderx_lmc_err_isr()
778 writeq(lmc_int, lmc->regs + LMC_INT); in thunderx_lmc_probe()
[all …]
/drivers/char/hw_random/
Dcavium-rng.c42 writeq(THUNDERX_RNM_RNG_EN | THUNDERX_RNM_ENT_EN, in cavium_rng_probe()
51 writeq(0, rng->control_status); in cavium_rng_probe()
72 writeq(0, rng->control_status); in cavium_rng_remove()
/drivers/net/ethernet/cavium/common/
Dcavium_ptp.c129 writeq(comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_adjfine()
277 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
280 writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP); in cavium_ptp_probe()
294 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
323 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_remove()
/drivers/net/ethernet/marvell/octeontx2/af/
Dptp.c138 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine()
183 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_probe()
187 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_probe()
218 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_remove()
/drivers/misc/ocxl/
Dmmio.c100 writeq(val, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_write64()
163 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_set64()
226 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()
230 writeq(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear64()
/drivers/pci/controller/
Dpci-thunder-pem.c46 writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD); in thunder_pem_bridge_read()
75 writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD); in thunder_pem_bridge_read()
227 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); in thunder_pem_bridge_write()
236 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD); in thunder_pem_bridge_write()
275 writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR); in thunder_pem_bridge_write()
/drivers/char/
Dhpet.c56 #define write_counter(V, MC) writeq(V, MC)
131 #ifndef writeq
132 static inline void writeq(unsigned long long v, void __iomem *addr) in writeq() function
426 writeq((readq(&timer->hpet_config) & ~Tn_INT_ENB_CNF_MASK), in hpet_release()
440 writeq(v, &timer->hpet_config); in hpet_release()
530 writeq(v, &timer->hpet_config); in hpet_ioctl_ieon()
557 writeq(g, &timer->hpet_config); in hpet_ioctl_ieon()
605 writeq(v, &timer->hpet_config); in hpet_ioctl_common()
642 writeq(v, &timer->hpet_config); in hpet_ioctl_common()
919 writeq(mcfg, &hpet->hpet_config); in hpet_alloc()
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_common.h154 #ifndef writeq
155 #define writeq writeq macro
156 static inline void writeq(u64 val, void __iomem *addr) in writeq() function
169 writeq(value, reg_addr + reg); in ixgbe_write_reg64()

123456