1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * These are the H.264 state controls for use with stateless H.264 4 * codec drivers. 5 * 6 * It turns out that these structs are not stable yet and will undergo 7 * more changes. So keep them private until they are stable and ready to 8 * become part of the official public API. 9 */ 10 11 #ifndef _H264_CTRLS_H_ 12 #define _H264_CTRLS_H_ 13 14 #include <linux/videodev2.h> 15 16 /* 17 * Maximum DPB size, as specified by section 'A.3.1 Level limits 18 * common to the Baseline, Main, and Extended profiles'. 19 */ 20 #define V4L2_H264_NUM_DPB_ENTRIES 16 21 22 #define V4L2_H264_REF_LIST_LEN (2 * V4L2_H264_NUM_DPB_ENTRIES) 23 24 /* Our pixel format isn't stable at the moment */ 25 #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ 26 27 /* 28 * This is put insanely high to avoid conflicting with controls that 29 * would be added during the phase where those controls are not 30 * stable. It should be fixed eventually. 31 */ 32 #define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) 33 #define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) 34 #define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) 35 #define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) 36 #define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) 37 #define V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (V4L2_CID_MPEG_BASE+1005) 38 #define V4L2_CID_MPEG_VIDEO_H264_START_CODE (V4L2_CID_MPEG_BASE+1006) 39 #define V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS (V4L2_CID_MPEG_BASE+1007) 40 41 enum v4l2_mpeg_video_h264_decode_mode { 42 V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED, 43 V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED, 44 }; 45 46 enum v4l2_mpeg_video_h264_start_code { 47 V4L2_MPEG_VIDEO_H264_START_CODE_NONE, 48 V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, 49 }; 50 51 #define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 52 #define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 53 #define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 54 #define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 55 #define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 56 #define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 57 58 #define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 59 #define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 60 #define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 61 #define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 62 #define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 63 #define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 64 #define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 65 66 struct v4l2_ctrl_h264_sps { 67 __u8 profile_idc; 68 __u8 constraint_set_flags; 69 __u8 level_idc; 70 __u8 seq_parameter_set_id; 71 __u8 chroma_format_idc; 72 __u8 bit_depth_luma_minus8; 73 __u8 bit_depth_chroma_minus8; 74 __u8 log2_max_frame_num_minus4; 75 __u8 pic_order_cnt_type; 76 __u8 log2_max_pic_order_cnt_lsb_minus4; 77 __u8 max_num_ref_frames; 78 __u8 num_ref_frames_in_pic_order_cnt_cycle; 79 __s32 offset_for_ref_frame[255]; 80 __s32 offset_for_non_ref_pic; 81 __s32 offset_for_top_to_bottom_field; 82 __u16 pic_width_in_mbs_minus1; 83 __u16 pic_height_in_map_units_minus1; 84 __u32 flags; 85 }; 86 87 #define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 88 #define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 89 #define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 90 #define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 91 #define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 92 #define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 93 #define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 94 #define V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT 0x0080 95 96 struct v4l2_ctrl_h264_pps { 97 __u8 pic_parameter_set_id; 98 __u8 seq_parameter_set_id; 99 __u8 num_slice_groups_minus1; 100 __u8 num_ref_idx_l0_default_active_minus1; 101 __u8 num_ref_idx_l1_default_active_minus1; 102 __u8 weighted_bipred_idc; 103 __s8 pic_init_qp_minus26; 104 __s8 pic_init_qs_minus26; 105 __s8 chroma_qp_index_offset; 106 __s8 second_chroma_qp_index_offset; 107 __u16 flags; 108 }; 109 110 struct v4l2_ctrl_h264_scaling_matrix { 111 __u8 scaling_list_4x4[6][16]; 112 __u8 scaling_list_8x8[6][64]; 113 }; 114 115 struct v4l2_h264_weight_factors { 116 __s16 luma_weight[32]; 117 __s16 luma_offset[32]; 118 __s16 chroma_weight[32][2]; 119 __s16 chroma_offset[32][2]; 120 }; 121 122 #define V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice) \ 123 ((((pps)->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && \ 124 ((slice)->slice_type == V4L2_H264_SLICE_TYPE_P || \ 125 (slice)->slice_type == V4L2_H264_SLICE_TYPE_SP)) || \ 126 ((pps)->weighted_bipred_idc == 1 && \ 127 (slice)->slice_type == V4L2_H264_SLICE_TYPE_B)) 128 129 struct v4l2_ctrl_h264_pred_weights { 130 __u16 luma_log2_weight_denom; 131 __u16 chroma_log2_weight_denom; 132 struct v4l2_h264_weight_factors weight_factors[2]; 133 }; 134 135 #define V4L2_H264_SLICE_TYPE_P 0 136 #define V4L2_H264_SLICE_TYPE_B 1 137 #define V4L2_H264_SLICE_TYPE_I 2 138 #define V4L2_H264_SLICE_TYPE_SP 3 139 #define V4L2_H264_SLICE_TYPE_SI 4 140 141 #define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x01 142 #define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x02 143 144 #define V4L2_H264_TOP_FIELD_REF 0x1 145 #define V4L2_H264_BOTTOM_FIELD_REF 0x2 146 #define V4L2_H264_FRAME_REF 0x3 147 148 struct v4l2_h264_reference { 149 __u8 fields; 150 151 /* Index into v4l2_ctrl_h264_decode_params.dpb[] */ 152 __u8 index; 153 }; 154 155 struct v4l2_ctrl_h264_slice_params { 156 /* Offset in bits to slice_data() from the beginning of this slice. */ 157 __u32 header_bit_size; 158 159 __u32 first_mb_in_slice; 160 161 __u8 slice_type; 162 __u8 colour_plane_id; 163 __u8 redundant_pic_cnt; 164 __u8 cabac_init_idc; 165 __s8 slice_qp_delta; 166 __s8 slice_qs_delta; 167 __u8 disable_deblocking_filter_idc; 168 __s8 slice_alpha_c0_offset_div2; 169 __s8 slice_beta_offset_div2; 170 __u8 num_ref_idx_l0_active_minus1; 171 __u8 num_ref_idx_l1_active_minus1; 172 173 __u8 reserved; 174 175 struct v4l2_h264_reference ref_pic_list0[V4L2_H264_REF_LIST_LEN]; 176 struct v4l2_h264_reference ref_pic_list1[V4L2_H264_REF_LIST_LEN]; 177 178 __u32 flags; 179 }; 180 181 #define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 182 #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 183 #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 184 #define V4L2_H264_DPB_ENTRY_FLAG_FIELD 0x08 185 186 struct v4l2_h264_dpb_entry { 187 __u64 reference_ts; 188 __u32 pic_num; 189 __u16 frame_num; 190 __u8 fields; 191 __u8 reserved[5]; 192 /* Note that field is indicated by v4l2_buffer.field */ 193 __s32 top_field_order_cnt; 194 __s32 bottom_field_order_cnt; 195 __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ 196 }; 197 198 #define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 199 #define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC 0x02 200 #define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD 0x04 201 202 struct v4l2_ctrl_h264_decode_params { 203 struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]; 204 __u16 nal_ref_idc; 205 __u16 frame_num; 206 __s32 top_field_order_cnt; 207 __s32 bottom_field_order_cnt; 208 __u16 idr_pic_id; 209 __u16 pic_order_cnt_lsb; 210 __s32 delta_pic_order_cnt_bottom; 211 __s32 delta_pic_order_cnt0; 212 __s32 delta_pic_order_cnt1; 213 /* Size in bits of dec_ref_pic_marking() syntax element. */ 214 __u32 dec_ref_pic_marking_bit_size; 215 /* Size in bits of pic order count syntax. */ 216 __u32 pic_order_cnt_bit_size; 217 __u32 slice_group_change_cycle; 218 219 __u32 reserved; 220 __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ 221 }; 222 223 #endif 224