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Searched refs:pll (Results 1 – 16 of 16) sorted by relevance

/sound/soc/codecs/
Dtlv320aic32x4-clk.c49 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); in clk_aic32x4_pll_prepare() local
51 return regmap_update_bits(pll->regmap, AIC32X4_PLLPR, in clk_aic32x4_pll_prepare()
57 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); in clk_aic32x4_pll_unprepare() local
59 regmap_update_bits(pll->regmap, AIC32X4_PLLPR, in clk_aic32x4_pll_unprepare()
65 struct clk_aic32x4 *pll = to_clk_aic32x4(hw); in clk_aic32x4_pll_is_prepared() local
70 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); in clk_aic32x4_pll_is_prepared()
77 static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll, in clk_aic32x4_pll_get_muldiv() argument
84 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); in clk_aic32x4_pll_get_muldiv()
90 ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val); in clk_aic32x4_pll_get_muldiv()
95 ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val); in clk_aic32x4_pll_get_muldiv()
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Dak4671.c472 u8 pll; in ak4671_set_dai_sysclk() local
474 pll = snd_soc_component_read(component, AK4671_PLL_MODE_SELECT0); in ak4671_set_dai_sysclk()
475 pll &= ~AK4671_PLL; in ak4671_set_dai_sysclk()
479 pll |= AK4671_PLL_11_2896MHZ; in ak4671_set_dai_sysclk()
482 pll |= AK4671_PLL_12MHZ; in ak4671_set_dai_sysclk()
485 pll |= AK4671_PLL_12_288MHZ; in ak4671_set_dai_sysclk()
488 pll |= AK4671_PLL_13MHZ; in ak4671_set_dai_sysclk()
491 pll |= AK4671_PLL_13_5MHZ; in ak4671_set_dai_sysclk()
494 pll |= AK4671_PLL_19_2MHZ; in ak4671_set_dai_sysclk()
497 pll |= AK4671_PLL_24MHZ; in ak4671_set_dai_sysclk()
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Dadav80x.c46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
65 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) argument
66 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) argument
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Dwm8955.c144 int Fref, int Fout, struct pll_factors *pll) in wm8955_pll_factors() argument
157 pll->outdiv = 1; in wm8955_pll_factors()
160 pll->outdiv = 0; in wm8955_pll_factors()
170 pll->n = Ndiv; in wm8955_pll_factors()
185 pll->k = K / 10; in wm8955_pll_factors()
187 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); in wm8955_pll_factors()
249 struct pll_factors pll; in wm8955_configure_clocking() local
283 clock_cfgs[sr].mclk, &pll); in wm8955_configure_clocking()
293 (pll.n << WM8955_N_SHIFT) | in wm8955_configure_clocking()
294 pll.k >> 18); in wm8955_configure_clocking()
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Dak4642.c340 u8 pll; in ak4642_dai_set_sysclk() local
345 pll = PLL2; in ak4642_dai_set_sysclk()
348 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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Dtscs454.c42 struct pll { struct
48 static inline void pll_init(struct pll *pll, int id) in pll_init() argument
50 pll->id = id; in pll_init()
51 mutex_init(&pll->lock); in pll_init()
55 struct pll *pll; member
61 struct pll *pll; member
131 struct pll pll1;
132 struct pll pll2;
660 static inline void reserve_pll(struct pll *pll) in reserve_pll() argument
662 mutex_lock(&pll->lock); in reserve_pll()
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Dtlv320aic32x4.c596 struct clk *pll; in aic32x4_set_dai_sysclk() local
598 pll = devm_clk_get(component->dev, "pll"); in aic32x4_set_dai_sysclk()
599 if (IS_ERR(pll)) in aic32x4_set_dai_sysclk()
600 return PTR_ERR(pll); in aic32x4_set_dai_sysclk()
602 mclk = clk_get_parent(pll); in aic32x4_set_dai_sysclk()
Dtwl6040.c55 int pll; member
887 if (unlikely(priv->pll == TWL6040_SYSCLK_SEL_HPPLL)) { in twl6040_hw_params()
923 ret = twl6040_set_pll(twl6040, priv->pll, priv->clk_in, priv->sysclk); in twl6040_prepare()
941 priv->pll = clk_id; in twl6040_set_dai_sysclk()
Dnau8822.c673 struct nau8822_pll *pll = &nau8822->pll; in nau8822_config_clkdiv() local
704 if (pll->mclk_scaler != div) { in nau8822_config_clkdiv()
729 struct nau8822_pll *pll_param = &nau8822->pll; in nau8822_set_pll()
Dnau8822.h208 struct nau8822_pll pll; member
Dnau8810.h281 struct nau8810_pll pll; member
Dmax98090.c2115 unsigned int pll; in max98090_pll_work() local
2141 pll = snd_soc_component_read( in max98090_pll_work()
2143 if (!(pll & M98090_ULK_MASK)) in max98090_pll_work()
Dnau8810.c572 struct nau8810_pll *pll_param = &nau8810->pll; in nau8810_set_pll()
/sound/soc/pxa/
Dpxa-ssp.c529 int pll; member
535 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
536 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
537 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
538 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
539 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
540 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
541 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
/sound/soc/ti/
Dj721e-evm.c562 struct clk *pll; in j721e_calculate_rate_range() local
566 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_44100]); in j721e_calculate_rate_range()
567 if (IS_ERR_OR_NULL(pll)) { in j721e_calculate_rate_range()
571 priv->pll_rates[J721E_CLK_PARENT_44100] = clk_get_rate(pll); in j721e_calculate_rate_range()
572 clk_put(pll); in j721e_calculate_rate_range()
575 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_48000]); in j721e_calculate_rate_range()
576 if (IS_ERR_OR_NULL(pll)) { in j721e_calculate_rate_range()
580 priv->pll_rates[J721E_CLK_PARENT_48000] = clk_get_rate(pll); in j721e_calculate_rate_range()
581 clk_put(pll); in j721e_calculate_rate_range()
/sound/soc/uniphier/
Daio-cpu.c130 struct uniphier_aio_pll *pll; in find_divider() local
138 pll = &aio->chip->plls[pll_id]; in find_divider()
140 if (pll->freq * mul[i] / div[i] == freq) in find_divider()