Searched refs:BrateCfg (Results 1 – 2 of 2) sorted by relevance
| /drivers/staging/rtl8188eu/hal/ |
| D | usb_halinit.c | 1255 u16 BrateCfg = 0; in rtw_hal_set_hwreg() local
1262 hal_set_brate_cfg(val, &BrateCfg); in rtw_hal_set_hwreg()
1263 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg); in rtw_hal_set_hwreg()
1270 BrateCfg = (BrateCfg | 0xd) & 0x15d; in rtw_hal_set_hwreg()
1271 haldata->BasicRateSet = BrateCfg; in rtw_hal_set_hwreg()
1273 BrateCfg |= 0x01; /* default enable 1M ACK rate */ in rtw_hal_set_hwreg()
1275 usb_write8(Adapter, REG_RRSR, BrateCfg & 0xff); in rtw_hal_set_hwreg()
1276 usb_write8(Adapter, REG_RRSR + 1, (BrateCfg >> 8) & 0xff); in rtw_hal_set_hwreg()
1280 while (BrateCfg > 0x1) { in rtw_hal_set_hwreg()
1281 BrateCfg >>= 1; in rtw_hal_set_hwreg()
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| /drivers/staging/rtl8723bs/hal/ |
| D | rtl8723b_hal_init.c | 3810 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0; in SetHwReg8723B() local
3814 HalSetBrateCfg(padapter, val, &BrateCfg); in SetHwReg8723B()
3815 input_b = BrateCfg; in SetHwReg8723B()
3818 BrateCfg |= rrsr_2g_force_mask; in SetHwReg8723B()
3819 BrateCfg &= rrsr_2g_allow_mask; in SetHwReg8723B()
3820 masked = BrateCfg; in SetHwReg8723B()
3823 BrateCfg |= (RRSR_11M|RRSR_5_5M|RRSR_1M); /* use 11M to send ACK */ in SetHwReg8723B()
3824 BrateCfg |= (RRSR_24M|RRSR_18M|RRSR_12M); /* CMCC_OFDM_ACK 12/18/24M */ in SetHwReg8723B()
3830 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0) in SetHwReg8723B()
3831 BrateCfg |= RRSR_6M; in SetHwReg8723B()
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