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Searched refs:DISPC_CONTROL2 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/omapdrm/dss/
Ddispc.c306 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
307 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
308 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
309 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
310 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
728 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
741 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
747 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
3472 DUMPREG(dispc, DISPC_CONTROL2); in dispc_dump_regs()
Ddispc.h22 #define DISPC_CONTROL2 0x0238 macro
/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc.h24 #define DISPC_CONTROL2 0x0238 macro
Ddispc.c208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
3420 DUMPREG(DISPC_CONTROL2); in dispc_dump_regs()