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Searched refs:cpt_read_csr64 (Results 1 – 5 of 5) sorted by relevance

/drivers/crypto/cavium/cpt/
Dcptvf_main.c369 vqx_ctl.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_CTL(0, 0)); in cptvf_write_vq_ctl()
378 vqx_dbell.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_doorbell()
389 vqx_inprg.u = cpt_read_csr64(cptvf->reg_base, CPTX_VQX_INPROG(0, 0)); in cptvf_write_vq_inprog()
398 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_done_numwait()
409 vqx_dwait.u = cpt_read_csr64(cptvf->reg_base, in cptvf_write_vq_done_timewait()
420 vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, in cptvf_enable_swerr_interrupts()
432 vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base, in cptvf_enable_mbox_interrupts()
444 vqx_done_ena.u = cpt_read_csr64(cptvf->reg_base, in cptvf_enable_done_interrupts()
456 vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, in cptvf_clear_dovf_intr()
468 vqx_misc_int.u = cpt_read_csr64(cptvf->reg_base, in cptvf_clear_irde_intr()
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Dcptpf_mbox.c41 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_qlen_for_vf()
54 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf)); in cpt_cfg_vq_priority()
77 pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q)); in cpt_bind_vq_to_grp()
96 mbx.msg = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 0)); in cpt_handle_mbox_intr()
97 mbx.data = cpt_read_csr64(cpt->reg_base, CPTX_PF_VFX_MBOXX(0, vf, 1)); in cpt_handle_mbox_intr()
151 intr = cpt_read_csr64(cpt->reg_base, CPTX_PF_MBOX_INTX(0, 0)); in cpt_mbox_intr_handler()
Dcptpf_main.c39 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); in cpt_disable_cores()
43 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); in cpt_disable_cores()
46 grp = cpt_read_csr64(cpt->reg_base, in cpt_disable_cores()
55 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); in cpt_disable_cores()
72 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); in cpt_enable_cores()
86 pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); in cpt_configure_group()
357 pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0)); in cpt_find_max_enabled_cores()
366 bist_sts.u = cpt_read_csr64(cpt->reg_base, in cpt_check_bist_status()
376 bist_sts.u = cpt_read_csr64(cpt->reg_base, in cpt_check_exe_bist_status()
393 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); in cpt_disable_all_cores()
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Dcptvf_mbox.c26 mbx.msg = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0)); in cptvf_handle_mbox_intr()
27 mbx.data = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1)); in cptvf_handle_mbox_intr()
Dcpt_common.h149 static inline u64 cpt_read_csr64(u8 __iomem *hw_addr, u64 offset) in cpt_read_csr64() function