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Searched refs:fp1 (Results 1 – 14 of 14) sorted by relevance

/drivers/tty/vt/
Dconmakehash.c83 int fp0, fp1, un0, un1; in main() local
152 fp1 = strtol(p, &p1, 0); in main()
161 fp1 = 0; in main()
170 if ( fp1 && (fp1 < fp0 || fp1 >= fontlen) ) in main()
174 tblname, fp1); in main()
178 if (fp1) in main()
186 for (i=fp0; i<=fp1; i++) in main()
208 tblname, fp0, fp1); in main()
211 if (un1 - un0 != fp1 - fp0) in main()
215 tblname, un0, un1, fp0, fp1); in main()
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/drivers/gpu/drm/gma500/
Doaktrail_device.c201 p->fp1 = PSB_RVDC32(MRST_FPA1); in oaktrail_save_display_registers()
316 PSB_WVDC32(p->fp1, MRST_FPA1); in oaktrail_restore_display_registers()
456 .fp1 = MRST_FPA1,
480 .fp1 = FPB1,
Dpsb_device.c253 .fp1 = FPA1,
277 .fp1 = FPB1,
Dgma_display.c594 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
643 REG_WRITE(map->fp1, crtc_state->saveFP1); in gma_crtc_restore()
644 REG_READ(map->fp1); in gma_crtc_restore()
Dpsb_intel_display.c315 fp = REG_READ(map->fp1); in psb_intel_crtc_clock_get()
324 fp = p->fp1; in psb_intel_crtc_clock_get()
Dcdv_device.c518 .fp1 = FPA1,
543 .fp1 = FPB1,
Dpsb_drv.h268 u32 fp1; member
302 u32 fp1; member
Dcdv_intel_display.c856 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
864 fp = p->fp1; in cdv_intel_crtc_clock_get()
Dmdfld_device.c441 .fp1 = MRST_FPA1,
/drivers/video/fbdev/intelfb/
Dintelfbhw.c1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1062 fp1 = &hw->fpb1; in intelfbhw_mode_to_hw()
1074 fp1 = &hw->fpa1; in intelfbhw_mode_to_hw()
1146 *fp1 = *fp0; in intelfbhw_mode_to_hw()
1281 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local
1305 fp1 = &hw->fpb1; in intelfbhw_program_mode()
1329 fp1 = &hw->fpa1; in intelfbhw_program_mode()
1404 OUTREG(fp1_reg, *fp1); in intelfbhw_program_mode()
/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h173 u32 fp1; member
Dintel_dpll_mgr.c420 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
433 intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
530 hw_state->fp1); in ibx_dump_hw_state()
4564 hw_state->fp1); in intel_dpll_dump_hw_state()
Dintel_display_debugfs.c940 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); in i915_shared_dplls_info()
Dintel_display.c7535 crtc_state->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
8263 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
8265 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
9550 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
10351 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_compute_dpll()
12149 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
13992 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); in intel_pipe_config_compare()