| /drivers/media/platform/qcom/venus/ |
| D | vdec.c | 91 find_format(struct venus_inst *inst, u32 pixfmt, u32 type) in find_format() argument
106 !venus_helper_check_codec(inst, fmt[i].pixfmt)) in find_format()
113 find_format_by_index(struct venus_inst *inst, unsigned int index, u32 type) in find_format_by_index() argument
128 venus_helper_check_codec(inst, fmt[i].pixfmt); in find_format_by_index()
142 vdec_try_fmt_common(struct venus_inst *inst, struct v4l2_format *f) in vdec_try_fmt_common() argument
152 fmt = find_format(inst, pixmp->pixelformat, f->type); in vdec_try_fmt_common()
160 fmt = find_format(inst, pixmp->pixelformat, f->type); in vdec_try_fmt_common()
165 pixmp->width = clamp(pixmp->width, frame_width_min(inst), in vdec_try_fmt_common()
166 frame_width_max(inst)); in vdec_try_fmt_common()
167 pixmp->height = clamp(pixmp->height, frame_height_min(inst), in vdec_try_fmt_common()
[all …]
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| D | venc.c | 63 find_format(struct venus_inst *inst, u32 pixfmt, u32 type) in find_format() argument
78 !venus_helper_check_codec(inst, fmt[i].pixfmt)) in find_format()
85 find_format_by_index(struct venus_inst *inst, unsigned int index, u32 type) in find_format_by_index() argument
100 venus_helper_check_codec(inst, fmt[i].pixfmt); in find_format_by_index()
151 struct venus_inst *inst = to_inst(file); in venc_enum_fmt() local
154 fmt = find_format_by_index(inst, f->index, f->type); in venc_enum_fmt()
167 venc_try_fmt_common(struct venus_inst *inst, struct v4l2_format *f) in venc_try_fmt_common() argument
177 fmt = find_format(inst, pixmp->pixelformat, f->type); in venc_try_fmt_common()
185 fmt = find_format(inst, pixmp->pixelformat, f->type); in venc_try_fmt_common()
190 pixmp->width = clamp(pixmp->width, frame_width_min(inst), in venc_try_fmt_common()
[all …]
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| D | hfi.c | 164 static int wait_session_msg(struct venus_inst *inst) in wait_session_msg() argument
168 ret = wait_for_completion_timeout(&inst->done, TIMEOUT); in wait_session_msg()
172 if (inst->error != HFI_ERR_NONE) in wait_session_msg()
178 int hfi_session_create(struct venus_inst *inst, const struct hfi_inst_ops *ops) in hfi_session_create() argument
180 struct venus_core *core = inst->core; in hfi_session_create()
185 inst->state = INST_UNINIT; in hfi_session_create()
186 init_completion(&inst->done); in hfi_session_create()
187 inst->ops = ops; in hfi_session_create()
190 list_add_tail(&inst->list, &core->instances); in hfi_session_create()
198 int hfi_session_init(struct venus_inst *inst, u32 pixfmt) in hfi_session_init() argument
[all …]
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| D | helpers.c | 28 bool venus_helper_check_codec(struct venus_inst *inst, u32 v4l2_pixfmt) in venus_helper_check_codec() argument
30 struct venus_core *core = inst->core; in venus_helper_check_codec()
31 u32 session_type = inst->session_type; in venus_helper_check_codec()
80 int venus_helper_queue_dpb_bufs(struct venus_inst *inst) in venus_helper_queue_dpb_bufs() argument
85 list_for_each_entry(buf, &inst->dpbbufs, list) { in venus_helper_queue_dpb_bufs()
93 ret = hfi_session_process_buf(inst, &fdata); in venus_helper_queue_dpb_bufs()
103 int venus_helper_free_dpb_bufs(struct venus_inst *inst) in venus_helper_free_dpb_bufs() argument
107 list_for_each_entry_safe(buf, n, &inst->dpbbufs, list) { in venus_helper_free_dpb_bufs()
109 dma_free_attrs(inst->core->dev, buf->size, buf->va, buf->da, in venus_helper_free_dpb_bufs()
114 INIT_LIST_HEAD(&inst->dpbbufs); in venus_helper_free_dpb_bufs()
[all …]
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| D | hfi_parser.h | 8 u32 hfi_parser(struct venus_core *core, struct venus_inst *inst,
15 static inline u32 get_cap(struct venus_inst *inst, u32 type, u32 which) in get_cap() argument
17 struct venus_core *core = inst->core; in get_cap()
22 caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type); in get_cap()
50 static inline u32 cap_min(struct venus_inst *inst, u32 type) in cap_min() argument
52 return get_cap(inst, type, WHICH_CAP_MIN); in cap_min()
55 static inline u32 cap_max(struct venus_inst *inst, u32 type) in cap_max() argument
57 return get_cap(inst, type, WHICH_CAP_MAX); in cap_max()
60 static inline u32 cap_step(struct venus_inst *inst, u32 type) in cap_step() argument
62 return get_cap(inst, type, WHICH_CAP_STEP); in cap_step()
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| D | helpers.h | 14 bool venus_helper_check_codec(struct venus_inst *inst, u32 v4l2_pixfmt);
15 struct vb2_v4l2_buffer *venus_helper_find_buf(struct venus_inst *inst,
17 void venus_helper_buffers_done(struct venus_inst *inst, unsigned int type,
23 int venus_helper_vb2_start_streaming(struct venus_inst *inst);
26 int venus_helper_get_bufreq(struct venus_inst *inst, u32 type,
30 int venus_helper_set_input_resolution(struct venus_inst *inst,
32 int venus_helper_set_output_resolution(struct venus_inst *inst,
35 int venus_helper_set_work_mode(struct venus_inst *inst, u32 mode);
36 int venus_helper_init_codec_freq_data(struct venus_inst *inst);
37 int venus_helper_set_num_bufs(struct venus_inst *inst, unsigned int input_bufs,
[all …]
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| D | venc_ctrls.c | 71 struct venus_inst *inst = ctrl_to_inst(ctrl); in venc_op_s_ctrl() local
72 struct venc_controls *ctr = &inst->controls.enc; in venc_op_s_ctrl()
85 mutex_lock(&inst->lock); in venc_op_s_ctrl()
86 if (inst->streamon_out && inst->streamon_cap) { in venc_op_s_ctrl()
91 ret = hfi_session_set_property(inst, ptype, &brate); in venc_op_s_ctrl()
93 mutex_unlock(&inst->lock); in venc_op_s_ctrl()
97 mutex_unlock(&inst->lock); in venc_op_s_ctrl()
190 mutex_lock(&inst->lock); in venc_op_s_ctrl()
191 if (inst->streamon_out && inst->streamon_cap) { in venc_op_s_ctrl()
193 ret = hfi_session_set_property(inst, ptype, &en); in venc_op_s_ctrl()
[all …]
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| D | hfi_msgs.c | 17 static void event_seq_changed(struct venus_core *core, struct venus_inst *inst, in event_seq_changed() argument
33 inst->error = HFI_ERR_NONE; in event_seq_changed()
40 inst->error = HFI_ERR_SESSION_INVALID_PARAMETER; in event_seq_changed()
48 inst->error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES; in event_seq_changed()
115 inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); in event_seq_changed()
119 struct venus_inst *inst, in event_release_buffer_ref() argument
133 inst->error = HFI_ERR_NONE; in event_release_buffer_ref()
134 inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); in event_release_buffer_ref()
150 event_session_error(struct venus_core *core, struct venus_inst *inst, in event_session_error() argument
158 if (!inst) in event_session_error()
[all …]
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| D | hfi.h | 100 void (*buf_done)(struct venus_inst *inst, unsigned int buf_type,
103 void (*event_notify)(struct venus_inst *inst, u32 event,
105 void (*flush_done)(struct venus_inst *inst);
114 int (*session_init)(struct venus_inst *inst, u32 session_type,
116 int (*session_end)(struct venus_inst *inst);
117 int (*session_abort)(struct venus_inst *inst);
118 int (*session_flush)(struct venus_inst *inst, u32 flush_mode);
119 int (*session_start)(struct venus_inst *inst);
120 int (*session_stop)(struct venus_inst *inst);
121 int (*session_continue)(struct venus_inst *inst);
[all …]
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| /drivers/media/platform/mtk-vcodec/venc/ |
| D | venc_h264_if.c | 158 static inline u32 h264_read_reg(struct venc_h264_inst *inst, u32 addr) in h264_read_reg() argument
160 return readl(inst->hw_base + addr); in h264_read_reg()
163 static unsigned int h264_get_profile(struct venc_h264_inst *inst, in h264_get_profile() argument
174 mtk_vcodec_err(inst, "unsupported CONSTRAINED_BASELINE"); in h264_get_profile()
177 mtk_vcodec_err(inst, "unsupported EXTENDED"); in h264_get_profile()
180 mtk_vcodec_debug(inst, "unsupported profile %d", profile); in h264_get_profile()
185 static unsigned int h264_get_level(struct venc_h264_inst *inst, in h264_get_level() argument
190 mtk_vcodec_err(inst, "unsupported 1B"); in h264_get_level()
219 mtk_vcodec_debug(inst, "unsupported level %d", level); in h264_get_level()
224 static void h264_enc_free_work_buf(struct venc_h264_inst *inst) in h264_enc_free_work_buf() argument
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| D | venc_vp8_if.c | 135 static inline u32 vp8_enc_read_reg(struct venc_vp8_inst *inst, u32 addr) in vp8_enc_read_reg() argument
137 return readl(inst->hw_base + addr); in vp8_enc_read_reg()
140 static void vp8_enc_free_work_buf(struct venc_vp8_inst *inst) in vp8_enc_free_work_buf() argument
144 mtk_vcodec_debug_enter(inst); in vp8_enc_free_work_buf()
148 if (inst->work_bufs[i].size == 0) in vp8_enc_free_work_buf()
150 mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]); in vp8_enc_free_work_buf()
153 mtk_vcodec_debug_leave(inst); in vp8_enc_free_work_buf()
156 static int vp8_enc_alloc_work_buf(struct venc_vp8_inst *inst) in vp8_enc_alloc_work_buf() argument
160 struct venc_vp8_vpu_buf *wb = inst->vsi->work_bufs; in vp8_enc_alloc_work_buf()
162 mtk_vcodec_debug_enter(inst); in vp8_enc_alloc_work_buf()
[all …]
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| /drivers/media/platform/mtk-vcodec/vdec/ |
| D | vdec_vp9_if.c | 206 static bool vp9_is_sf_ref_fb(struct vdec_vp9_inst *inst, struct vdec_fb *fb) in vp9_is_sf_ref_fb() argument
209 struct vdec_vp9_vsi *vsi = inst->vsi; in vp9_is_sf_ref_fb()
219 *inst, void *addr) in vp9_rm_from_fb_use_list()
224 list_for_each_entry(node, &inst->fb_use_list, list) { in vp9_rm_from_fb_use_list()
228 &inst->available_fb_node_list); in vp9_rm_from_fb_use_list()
236 static void vp9_add_to_fb_free_list(struct vdec_vp9_inst *inst, in vp9_add_to_fb_free_list() argument
242 node = list_first_entry_or_null(&inst->available_fb_node_list, in vp9_add_to_fb_free_list()
247 list_move_tail(&node->list, &inst->fb_free_list); in vp9_add_to_fb_free_list()
250 mtk_vcodec_debug(inst, "No free fb node"); in vp9_add_to_fb_free_list()
262 static void vp9_ref_cnt_fb(struct vdec_vp9_inst *inst, int *idx, in vp9_ref_cnt_fb() argument
[all …]
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| D | vdec_vp8_if.c | 168 static void get_hw_reg_base(struct vdec_vp8_inst *inst) in get_hw_reg_base() argument
170 inst->reg_base.top = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_TOP); in get_hw_reg_base()
171 inst->reg_base.cm = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_CM); in get_hw_reg_base()
172 inst->reg_base.hwd = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWD); in get_hw_reg_base()
173 inst->reg_base.sys = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_SYS); in get_hw_reg_base()
174 inst->reg_base.misc = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_MISC); in get_hw_reg_base()
175 inst->reg_base.ld = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_LD); in get_hw_reg_base()
176 inst->reg_base.hwb = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWB); in get_hw_reg_base()
179 static void write_hw_segmentation_data(struct vdec_vp8_inst *inst) in write_hw_segmentation_data() argument
184 void __iomem *cm = inst->reg_base.cm; in write_hw_segmentation_data()
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| D | vdec_h264_if.c | 140 static int allocate_predication_buf(struct vdec_h264_inst *inst) in allocate_predication_buf() argument
144 inst->pred_buf.size = BUF_PREDICTION_SZ; in allocate_predication_buf()
145 err = mtk_vcodec_mem_alloc(inst->ctx, &inst->pred_buf); in allocate_predication_buf()
147 mtk_vcodec_err(inst, "failed to allocate ppl buf"); in allocate_predication_buf()
151 inst->vsi->pred_buf_dma = inst->pred_buf.dma_addr; in allocate_predication_buf()
155 static void free_predication_buf(struct vdec_h264_inst *inst) in free_predication_buf() argument
159 mtk_vcodec_debug_enter(inst); in free_predication_buf()
161 inst->vsi->pred_buf_dma = 0; in free_predication_buf()
162 mem = &inst->pred_buf; in free_predication_buf()
164 mtk_vcodec_mem_free(inst->ctx, mem); in free_predication_buf()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv25.c | 37 &chan->inst); in nv25_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
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| D | nv35.c | 37 &chan->inst); in nv35_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv35_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv35_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv35_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv35_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv35_gr_chan_new()
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| D | nv34.c | 37 &chan->inst); in nv34_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060); in nv34_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080); in nv34_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000); in nv34_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001); in nv34_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000); in nv34_gr_chan_new()
[all …]
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| D | nv2a.c | 37 &chan->inst); in nv2a_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv2a_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); in nv2a_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv2a_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv2a_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv2a_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv2a_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0490, 0x00000111); in nv2a_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04a8, 0x44400000); in nv2a_gr_chan_new()
50 nvkm_wo32(chan->inst, i, 0x00030303); in nv2a_gr_chan_new()
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| D | nv30.c | 38 &chan->inst); in nv30_gr_chan_new()
42 nvkm_kmap(chan->inst); in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
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| /drivers/soc/mediatek/ |
| D | mtk-cmdq-helper.c | 170 struct cmdq_instruction inst) in cmdq_pkt_append_command() argument
190 *cmd_ptr = inst; in cmdq_pkt_append_command()
198 struct cmdq_instruction inst; in cmdq_pkt_write() local
200 inst.op = CMDQ_CODE_WRITE; in cmdq_pkt_write()
201 inst.value = value; in cmdq_pkt_write()
202 inst.offset = offset; in cmdq_pkt_write()
203 inst.subsys = subsys; in cmdq_pkt_write()
205 return cmdq_pkt_append_command(pkt, inst); in cmdq_pkt_write()
212 struct cmdq_instruction inst = { {0} }; in cmdq_pkt_write_mask() local
217 inst.op = CMDQ_CODE_MASK; in cmdq_pkt_write_mask()
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| /drivers/phy/mediatek/ |
| D | phy-mtk-xsphy.c | 117 struct xsphy_instance *inst) in u2_phy_slew_rate_calibrate() argument
119 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
125 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
176 inst->index, fm_out, calib_val, in u2_phy_slew_rate_calibrate()
192 struct xsphy_instance *inst) in u2_phy_instance_init() argument
194 void __iomem *pbase = inst->port_base; in u2_phy_instance_init()
208 struct xsphy_instance *inst) in u2_phy_instance_power_on() argument
210 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_on()
211 u32 index = inst->index; in u2_phy_instance_power_on()
227 struct xsphy_instance *inst) in u2_phy_instance_power_off() argument
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_mpc.h | 45 #define MPC_REG_LIST_DCN3_0(inst)\ argument
46 MPC_COMMON_REG_LIST_DCN1_0(inst),\
47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
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| D | dcn30_mmhubbub.h | 41 #define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \ argument
42 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
44 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
45 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
46 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
47 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
48 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
49 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
50 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
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| D | dcn30_optc.h | 32 #define OPTC_COMMON_REG_LIST_DCN3_BASE(inst) \ argument
33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.h | 33 #define MPC_REG_LIST_DCN2_0(inst)\ argument
34 MPC_COMMON_REG_LIST_DCN1_0(inst),\
35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
[all …]
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