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Searched refs:nvif_rd32 (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/nouveau/
Dnouveau_backlight.c72 int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & in nv40_get_intensity()
85 int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); in nv40_set_intensity()
107 if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) in nv40_backlight_init()
126 val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); in nv50_get_intensity()
161 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); in nva3_get_intensity()
162 val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); in nva3_get_intensity()
179 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); in nva3_set_intensity()
206 if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1))) in nv50_backlight_init()
Dnouveau_svm.c438 const u32 instlo = nvif_rd32(memory, offset + 0x00); in nouveau_svm_fault_cache()
439 const u32 insthi = nvif_rd32(memory, offset + 0x04); in nouveau_svm_fault_cache()
440 const u32 addrlo = nvif_rd32(memory, offset + 0x08); in nouveau_svm_fault_cache()
441 const u32 addrhi = nvif_rd32(memory, offset + 0x0c); in nouveau_svm_fault_cache()
442 const u32 timelo = nvif_rd32(memory, offset + 0x10); in nouveau_svm_fault_cache()
443 const u32 timehi = nvif_rd32(memory, offset + 0x14); in nouveau_svm_fault_cache()
444 const u32 engine = nvif_rd32(memory, offset + 0x18); in nouveau_svm_fault_cache()
445 const u32 info = nvif_rd32(memory, offset + 0x1c); in nouveau_svm_fault_cache()
639 buffer->put = nvif_rd32(device, buffer->putaddr); in nouveau_svm_fault()
640 buffer->get = nvif_rd32(device, buffer->getaddr); in nouveau_svm_fault()
[all …]
Dnouveau_dma.c45 val = nvif_rd32(&chan->user, chan->user_get); in READ_GET()
47 val |= (uint64_t)nvif_rd32(&chan->user, chan->user_get_hi) << 32; in READ_GET()
101 uint32_t get = nvif_rd32(&chan->user, 0x88); in nv50_dma_push_wait()
Dnouveau_led.c44 div = nvif_rd32(device, 0x61c880) & 0x00ffffff; in nouveau_led_get_brightness()
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
Dnouveau_bios.c239 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in call_lvds_script()
335 return nvif_rd32(device, 0x001800) & 0x0000000f; in get_fp_strap()
338 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; in get_fp_strap()
340 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; in get_fp_strap()
670 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in run_tmds_table()
1952 nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); in load_nv17_hwsq_ucode_entry()
Dnouveau_debugfs.c63 nvif_rd32(&drm->client.device.object, 0x101000)); in nouveau_debugfs_strap_peek()
/drivers/gpu/drm/nouveau/nvif/
Duserc361.c30 hi = nvif_rd32(&user->object, 0x084); in nvif_userc361_time()
31 lo = nvif_rd32(&user->object, 0x080); in nvif_userc361_time()
32 } while (hi != nvif_rd32(&user->object, 0x084)); in nvif_userc361_time()
/drivers/gpu/drm/nouveau/dispnv04/
Darb.c202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb()
222 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; in nv04_update_arb()
223 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; in nv04_update_arb()
Ddac.c84 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) in sample_load_twice()
90 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) in sample_load_twice()
96 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) in sample_load_twice()
264 saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2); in nv17_dac_sample_load()
268 saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4); in nv17_dac_sample_load()
Dhw.h66 val = nvif_rd32(device, reg); in NVReadCRTC()
86 val = nvif_rd32(device, reg); in NVReadRAMDAC()
265 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28)); in nv_heads_tied()
Dhw.c178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
749 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) in nv_load_state_ext()
753 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) in nv_load_state_ext()
Dtvnv17.h140 return nvif_rd32(&device->object, reg); in nv_read_ptv()
Doverlay.c433 nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); in nv04_update_plane()
Ddfp.c340 if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) in nv04_dfp_mode_set()
/drivers/gpu/drm/nouveau/include/nvif/
Dobject.h61 #define nvif_rd32(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); }) macro
67 u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
119 #define NVIF_RD32_(p,o,dr) nvif_rd32((p), (o) + (dr))
/drivers/gpu/drm/nouveau/dispnv50/
Dsorc37d.c45 u32 tmp = nvif_rd32(&disp->caps, 0x000144 + (or * 8)); in sorc37d_get_caps()
Ddisp.c142 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()
2708 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; in nv50_display_create()
2711 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; in nv50_display_create()