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Searched refs:octeon_read_csr (Results 1 – 7 of 7) sorted by relevance

/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_device.c320 intr = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in lio_cn6xxx_setup_oq_regs()
325 intr = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in lio_cn6xxx_setup_oq_regs()
334 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); in lio_cn6xxx_enable_io_queues()
338 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_enable_io_queues()
342 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_enable_io_queues()
356 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); in lio_cn6xxx_disable_io_queues()
362 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
364 d32 = octeon_read_csr(oct, CN6XXX_SLI_PORT_IN_RST_IQ); in lio_cn6xxx_disable_io_queues()
373 d32 = octeon_read_csr(oct, CN6XXX_SLI_IQ_DOORBELL(i)); in lio_cn6xxx_disable_io_queues()
377 mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in lio_cn6xxx_disable_io_queues()
[all …]
Dcn23xx_pf_device.c125 CVM_CAST64(octeon_read_csr( in cn23xx_dump_pf_initialized_regs()
155 CVM_CAST64(octeon_read_csr in cn23xx_dump_pf_initialized_regs()
179 CVM_CAST64(octeon_read_csr in cn23xx_dump_pf_initialized_regs()
184 CVM_CAST64(octeon_read_csr( in cn23xx_dump_pf_initialized_regs()
494 reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_pf_setup_global_output_regs()
655 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
663 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
857 reg_val = octeon_read_csr( in cn23xx_enable_io_queues()
935 WRITE_ONCE(d32, octeon_read_csr( in cn23xx_disable_io_queues()
1150 oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff; in cn23xx_get_pcie_qlmport()
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Dlio_ethtool.c2882 CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2885 CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2888 CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2891 CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2894 CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2897 CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2900 octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG)); in cn6xxx_read_csr_reg()
2904 CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct, in cn6xxx_read_csr_reg()
2908 octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1)); in cn6xxx_read_csr_reg()
2910 octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64)); in cn6xxx_read_csr_reg()
[all …]
Dcn23xx_vf_device.c161 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); in cn23xx_vf_setup_global_output_regs()
166 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_vf_setup_global_output_regs()
348 reg_val = octeon_read_csr( in cn23xx_enable_vf_io_queues()
Docteon_droq.c837 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB); in octeon_enable_irq()
840 value = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB); in octeon_enable_irq()
Docteon_device.h746 #define octeon_read_csr(oct_dev, reg_off) \ macro
Docteon_device.c1002 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); in octeon_set_droq_pkt_op()