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Searched refs:pps_idx (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/
Di915_reg.h4999 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ argument
5001 (pps_idx) * 0x100)
5004 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) argument
5031 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) argument
5041 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) argument
5052 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) argument
5057 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) argument
/drivers/gpu/drm/i915/display/
Dintel_dp.c1111 int pps_idx = 0; in intel_pps_get_registers() local
1116 pps_idx = bxt_power_sequencer_idx(intel_dp); in intel_pps_get_registers()
1118 pps_idx = vlv_power_sequencer_pipe(intel_dp); in intel_pps_get_registers()
1120 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
1121 regs->pp_stat = PP_STATUS(pps_idx); in intel_pps_get_registers()
1122 regs->pp_on = PP_ON_DELAYS(pps_idx); in intel_pps_get_registers()
1123 regs->pp_off = PP_OFF_DELAYS(pps_idx); in intel_pps_get_registers()
1129 regs->pp_div = PP_DIVISOR(pps_idx); in intel_pps_get_registers()
Dintel_display.c16852 int pps_idx; in intel_pps_unlock_regs_wa() local
16865 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { in intel_pps_unlock_regs_wa()
16866 u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)); in intel_pps_unlock_regs_wa()
16869 intel_de_write(dev_priv, PP_CONTROL(pps_idx), val); in intel_pps_unlock_regs_wa()