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Searched refs:wave (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2982 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2985 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2993 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2997 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
3007 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v6_0_read_wave_data() argument
3011 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
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Damdgpu_gfx.h207 uint32_t wave, uint32_t *dst, int *no_fields);
209 uint32_t wave, uint32_t thread, uint32_t start,
212 uint32_t wave, uint32_t start, uint32_t size,
Dgfx_v7_0.c4149 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4152 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4160 uint32_t wave, uint32_t thread, in wave_read_regs() argument
4164 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4174 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument
4178 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4179 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4180 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4181 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4182 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
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Damdgpu_debugfs.c880 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
890 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
911 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
972 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
982 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read()
1005 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1008 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
Dgfx_v8_0.c5228 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5231 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5239 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5243 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5253 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v8_0_read_wave_data() argument
5257 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5258 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5259 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5260 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5261 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
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Dgfx_v9_0.c2013 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2016 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2024 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2028 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
2038 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v9_0_read_wave_data() argument
2042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
2043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
2044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
2045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
2046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
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Dgfx_v10_0.c4143 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
4146 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4151 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
4156 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4164 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v10_0_read_wave_data() argument
4173 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
4174 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
4175 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
4176 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data()
4177 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
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/drivers/gpu/ipu-v3/
Dipu-dc.c120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
/drivers/media/rc/
DKconfig402 wave and pulses.