1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clock-latency = <61036>; /* two CLK32 periods */ 77 clocks = <&clks IMX7D_CLK_ARM>; 78 cpu-idle-states = <&cpu_sleep_wait>; 79 }; 80 }; 81 82 ckil: clock-cki { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32768>; 86 clock-output-names = "ckil"; 87 }; 88 89 osc: clock-osc { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <24000000>; 93 clock-output-names = "osc"; 94 }; 95 96 usbphynop1: usbphynop1 { 97 compatible = "usb-nop-xceiv"; 98 clocks = <&clks IMX7D_USB_PHY1_CLK>; 99 clock-names = "main_clk"; 100 #phy-cells = <0>; 101 }; 102 103 usbphynop3: usbphynop3 { 104 compatible = "usb-nop-xceiv"; 105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 106 clock-names = "main_clk"; 107 power-domains = <&pgc_hsic_phy>; 108 #phy-cells = <0>; 109 }; 110 111 pmu { 112 compatible = "arm,cortex-a7-pmu"; 113 interrupt-parent = <&gpc>; 114 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 115 interrupt-affinity = <&cpu0>; 116 }; 117 118 replicator { 119 /* 120 * non-configurable replicators don't show up on the 121 * AMBA bus. As such no need to add "arm,primecell" 122 */ 123 compatible = "arm,coresight-static-replicator"; 124 125 out-ports { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 /* replicator output ports */ 129 port@0 { 130 reg = <0>; 131 replicator_out_port0: endpoint { 132 remote-endpoint = <&tpiu_in_port>; 133 }; 134 }; 135 136 port@1 { 137 reg = <1>; 138 replicator_out_port1: endpoint { 139 remote-endpoint = <&etr_in_port>; 140 }; 141 }; 142 }; 143 144 in-ports { 145 port { 146 replicator_in_port0: endpoint { 147 remote-endpoint = <&etf_out_port>; 148 }; 149 }; 150 }; 151 }; 152 153 timer { 154 compatible = "arm,armv7-timer"; 155 interrupt-parent = <&intc>; 156 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 160 }; 161 162 soc { 163 #address-cells = <1>; 164 #size-cells = <1>; 165 compatible = "simple-bus"; 166 interrupt-parent = <&gpc>; 167 ranges; 168 169 funnel@30041000 { 170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 171 reg = <0x30041000 0x1000>; 172 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 173 clock-names = "apb_pclk"; 174 175 ca_funnel_in_ports: in-ports { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 port@0 { 180 reg = <0>; 181 ca_funnel_in_port0: endpoint { 182 remote-endpoint = <&etm0_out_port>; 183 }; 184 }; 185 186 /* the other input ports are not connect to anything */ 187 }; 188 189 out-ports { 190 port { 191 ca_funnel_out_port0: endpoint { 192 remote-endpoint = <&hugo_funnel_in_port0>; 193 }; 194 }; 195 196 }; 197 }; 198 199 etm@3007c000 { 200 compatible = "arm,coresight-etm3x", "arm,primecell"; 201 reg = <0x3007c000 0x1000>; 202 cpu = <&cpu0>; 203 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 204 clock-names = "apb_pclk"; 205 206 out-ports { 207 port { 208 etm0_out_port: endpoint { 209 remote-endpoint = <&ca_funnel_in_port0>; 210 }; 211 }; 212 }; 213 }; 214 215 funnel@30083000 { 216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 217 reg = <0x30083000 0x1000>; 218 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 219 clock-names = "apb_pclk"; 220 221 in-ports { 222 #address-cells = <1>; 223 #size-cells = <0>; 224 225 port@0 { 226 reg = <0>; 227 hugo_funnel_in_port0: endpoint { 228 remote-endpoint = <&ca_funnel_out_port0>; 229 }; 230 }; 231 232 port@1 { 233 reg = <1>; 234 hugo_funnel_in_port1: endpoint { 235 /* M4 input */ 236 }; 237 }; 238 /* the other input ports are not connect to anything */ 239 }; 240 241 out-ports { 242 port { 243 hugo_funnel_out_port0: endpoint { 244 remote-endpoint = <&etf_in_port>; 245 }; 246 }; 247 }; 248 }; 249 250 etf@30084000 { 251 compatible = "arm,coresight-tmc", "arm,primecell"; 252 reg = <0x30084000 0x1000>; 253 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 254 clock-names = "apb_pclk"; 255 256 in-ports { 257 port { 258 etf_in_port: endpoint { 259 remote-endpoint = <&hugo_funnel_out_port0>; 260 }; 261 }; 262 }; 263 264 out-ports { 265 port { 266 etf_out_port: endpoint { 267 remote-endpoint = <&replicator_in_port0>; 268 }; 269 }; 270 }; 271 }; 272 273 etr@30086000 { 274 compatible = "arm,coresight-tmc", "arm,primecell"; 275 reg = <0x30086000 0x1000>; 276 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 277 clock-names = "apb_pclk"; 278 279 in-ports { 280 port { 281 etr_in_port: endpoint { 282 remote-endpoint = <&replicator_out_port1>; 283 }; 284 }; 285 }; 286 }; 287 288 tpiu@30087000 { 289 compatible = "arm,coresight-tpiu", "arm,primecell"; 290 reg = <0x30087000 0x1000>; 291 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 292 clock-names = "apb_pclk"; 293 294 in-ports { 295 port { 296 tpiu_in_port: endpoint { 297 remote-endpoint = <&replicator_out_port0>; 298 }; 299 }; 300 }; 301 }; 302 303 intc: interrupt-controller@31001000 { 304 compatible = "arm,cortex-a7-gic"; 305 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 306 #interrupt-cells = <3>; 307 interrupt-controller; 308 interrupt-parent = <&intc>; 309 reg = <0x31001000 0x1000>, 310 <0x31002000 0x2000>, 311 <0x31004000 0x2000>, 312 <0x31006000 0x2000>; 313 }; 314 315 aips1: bus@30000000 { 316 compatible = "fsl,aips-bus", "simple-bus"; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 reg = <0x30000000 0x400000>; 320 ranges; 321 322 gpio1: gpio@30200000 { 323 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 324 reg = <0x30200000 0x10000>; 325 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 326 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 327 gpio-controller; 328 #gpio-cells = <2>; 329 interrupt-controller; 330 #interrupt-cells = <2>; 331 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 332 }; 333 334 gpio2: gpio@30210000 { 335 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 336 reg = <0x30210000 0x10000>; 337 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 gpio-ranges = <&iomuxc 0 13 32>; 344 }; 345 346 gpio3: gpio@30220000 { 347 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 348 reg = <0x30220000 0x10000>; 349 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 351 gpio-controller; 352 #gpio-cells = <2>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 gpio-ranges = <&iomuxc 0 45 29>; 356 }; 357 358 gpio4: gpio@30230000 { 359 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 360 reg = <0x30230000 0x10000>; 361 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 363 gpio-controller; 364 #gpio-cells = <2>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 gpio-ranges = <&iomuxc 0 74 24>; 368 }; 369 370 gpio5: gpio@30240000 { 371 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 372 reg = <0x30240000 0x10000>; 373 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 375 gpio-controller; 376 #gpio-cells = <2>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 gpio-ranges = <&iomuxc 0 98 18>; 380 }; 381 382 gpio6: gpio@30250000 { 383 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 384 reg = <0x30250000 0x10000>; 385 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 gpio-ranges = <&iomuxc 0 116 23>; 392 }; 393 394 gpio7: gpio@30260000 { 395 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 396 reg = <0x30260000 0x10000>; 397 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 399 gpio-controller; 400 #gpio-cells = <2>; 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 gpio-ranges = <&iomuxc 0 139 16>; 404 }; 405 406 wdog1: watchdog@30280000 { 407 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 408 reg = <0x30280000 0x10000>; 409 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 411 }; 412 413 wdog2: watchdog@30290000 { 414 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 415 reg = <0x30290000 0x10000>; 416 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 418 status = "disabled"; 419 }; 420 421 wdog3: watchdog@302a0000 { 422 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 423 reg = <0x302a0000 0x10000>; 424 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 426 status = "disabled"; 427 }; 428 429 wdog4: watchdog@302b0000 { 430 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 431 reg = <0x302b0000 0x10000>; 432 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 434 status = "disabled"; 435 }; 436 437 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 438 compatible = "fsl,imx7d-iomuxc-lpsr"; 439 reg = <0x302c0000 0x10000>; 440 fsl,input-sel = <&iomuxc>; 441 }; 442 443 gpt1: timer@302d0000 { 444 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 445 reg = <0x302d0000 0x10000>; 446 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 448 <&clks IMX7D_GPT1_ROOT_CLK>; 449 clock-names = "ipg", "per"; 450 }; 451 452 gpt2: timer@302e0000 { 453 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 454 reg = <0x302e0000 0x10000>; 455 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 457 <&clks IMX7D_GPT2_ROOT_CLK>; 458 clock-names = "ipg", "per"; 459 status = "disabled"; 460 }; 461 462 gpt3: timer@302f0000 { 463 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 464 reg = <0x302f0000 0x10000>; 465 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 467 <&clks IMX7D_GPT3_ROOT_CLK>; 468 clock-names = "ipg", "per"; 469 status = "disabled"; 470 }; 471 472 gpt4: timer@30300000 { 473 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 474 reg = <0x30300000 0x10000>; 475 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 477 <&clks IMX7D_GPT4_ROOT_CLK>; 478 clock-names = "ipg", "per"; 479 status = "disabled"; 480 }; 481 482 kpp: keypad@30320000 { 483 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 484 reg = <0x30320000 0x10000>; 485 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 487 status = "disabled"; 488 }; 489 490 iomuxc: pinctrl@30330000 { 491 compatible = "fsl,imx7d-iomuxc"; 492 reg = <0x30330000 0x10000>; 493 }; 494 495 gpr: iomuxc-gpr@30340000 { 496 compatible = "fsl,imx7d-iomuxc-gpr", 497 "fsl,imx6q-iomuxc-gpr", "syscon", 498 "simple-mfd"; 499 reg = <0x30340000 0x10000>; 500 501 mux: mux-controller { 502 compatible = "mmio-mux"; 503 #mux-control-cells = <1>; 504 mux-reg-masks = <0x14 0x00000010>; 505 }; 506 507 video_mux: csi-mux { 508 compatible = "video-mux"; 509 mux-controls = <&mux 0>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 status = "disabled"; 513 514 port@0 { 515 reg = <0>; 516 }; 517 518 port@1 { 519 reg = <1>; 520 521 csi_mux_from_mipi_vc0: endpoint { 522 remote-endpoint = <&mipi_vc0_to_csi_mux>; 523 }; 524 }; 525 526 port@2 { 527 reg = <2>; 528 529 csi_mux_to_csi: endpoint { 530 remote-endpoint = <&csi_from_csi_mux>; 531 }; 532 }; 533 }; 534 }; 535 536 ocotp: efuse@30350000 { 537 #address-cells = <1>; 538 #size-cells = <1>; 539 compatible = "fsl,imx7d-ocotp", "syscon"; 540 reg = <0x30350000 0x10000>; 541 clocks = <&clks IMX7D_OCOTP_CLK>; 542 543 tempmon_calib: calib@3c { 544 reg = <0x3c 0x4>; 545 }; 546 547 fuse_grade: fuse-grade@10 { 548 reg = <0x10 0x4>; 549 }; 550 }; 551 552 anatop: anatop@30360000 { 553 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 554 "syscon", "simple-mfd"; 555 reg = <0x30360000 0x10000>; 556 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 558 559 reg_1p0d: regulator-vdd1p0d { 560 compatible = "fsl,anatop-regulator"; 561 regulator-name = "vdd1p0d"; 562 regulator-min-microvolt = <800000>; 563 regulator-max-microvolt = <1200000>; 564 anatop-reg-offset = <0x210>; 565 anatop-vol-bit-shift = <8>; 566 anatop-vol-bit-width = <5>; 567 anatop-min-bit-val = <8>; 568 anatop-min-voltage = <800000>; 569 anatop-max-voltage = <1200000>; 570 anatop-enable-bit = <0>; 571 }; 572 573 reg_1p2: regulator-vdd1p2 { 574 compatible = "fsl,anatop-regulator"; 575 regulator-name = "vdd1p2"; 576 regulator-min-microvolt = <1100000>; 577 regulator-max-microvolt = <1300000>; 578 anatop-reg-offset = <0x220>; 579 anatop-vol-bit-shift = <8>; 580 anatop-vol-bit-width = <5>; 581 anatop-min-bit-val = <0x14>; 582 anatop-min-voltage = <1100000>; 583 anatop-max-voltage = <1300000>; 584 anatop-enable-bit = <0>; 585 }; 586 587 tempmon: tempmon { 588 compatible = "fsl,imx7d-tempmon"; 589 interrupt-parent = <&gpc>; 590 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 591 fsl,tempmon = <&anatop>; 592 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 593 nvmem-cell-names = "calib", "temp_grade"; 594 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 595 }; 596 }; 597 598 snvs: snvs@30370000 { 599 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 600 reg = <0x30370000 0x10000>; 601 602 snvs_rtc: snvs-rtc-lp { 603 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 604 regmap = <&snvs>; 605 offset = <0x34>; 606 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&clks IMX7D_SNVS_CLK>; 609 clock-names = "snvs-rtc"; 610 }; 611 612 snvs_pwrkey: snvs-powerkey { 613 compatible = "fsl,sec-v4.0-pwrkey"; 614 regmap = <&snvs>; 615 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&clks IMX7D_SNVS_CLK>; 617 clock-names = "snvs-pwrkey"; 618 linux,keycode = <KEY_POWER>; 619 wakeup-source; 620 status = "disabled"; 621 }; 622 }; 623 624 clks: clock-controller@30380000 { 625 compatible = "fsl,imx7d-ccm"; 626 reg = <0x30380000 0x10000>; 627 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 629 #clock-cells = <1>; 630 clocks = <&ckil>, <&osc>; 631 clock-names = "ckil", "osc"; 632 }; 633 634 src: reset-controller@30390000 { 635 compatible = "fsl,imx7d-src", "syscon"; 636 reg = <0x30390000 0x10000>; 637 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 638 #reset-cells = <1>; 639 }; 640 641 gpc: gpc@303a0000 { 642 compatible = "fsl,imx7d-gpc"; 643 reg = <0x303a0000 0x10000>; 644 interrupt-controller; 645 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 646 #interrupt-cells = <3>; 647 interrupt-parent = <&intc>; 648 #power-domain-cells = <1>; 649 650 pgc { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 654 pgc_mipi_phy: power-domain@0 { 655 #power-domain-cells = <0>; 656 reg = <0>; 657 power-supply = <®_1p0d>; 658 }; 659 660 pgc_pcie_phy: power-domain@1 { 661 #power-domain-cells = <0>; 662 reg = <1>; 663 power-supply = <®_1p0d>; 664 }; 665 666 pgc_hsic_phy: power-domain@2 { 667 #power-domain-cells = <0>; 668 reg = <2>; 669 power-supply = <®_1p2>; 670 }; 671 }; 672 }; 673 }; 674 675 aips2: bus@30400000 { 676 compatible = "fsl,aips-bus", "simple-bus"; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 reg = <0x30400000 0x400000>; 680 ranges; 681 682 adc1: adc@30610000 { 683 compatible = "fsl,imx7d-adc"; 684 reg = <0x30610000 0x10000>; 685 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 687 clock-names = "adc"; 688 #io-channel-cells = <1>; 689 status = "disabled"; 690 }; 691 692 adc2: adc@30620000 { 693 compatible = "fsl,imx7d-adc"; 694 reg = <0x30620000 0x10000>; 695 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 697 clock-names = "adc"; 698 #io-channel-cells = <1>; 699 status = "disabled"; 700 }; 701 702 ecspi4: spi@30630000 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 706 reg = <0x30630000 0x10000>; 707 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 709 <&clks IMX7D_ECSPI4_ROOT_CLK>; 710 clock-names = "ipg", "per"; 711 status = "disabled"; 712 }; 713 714 pwm1: pwm@30660000 { 715 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 716 reg = <0x30660000 0x10000>; 717 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 719 <&clks IMX7D_PWM1_ROOT_CLK>; 720 clock-names = "ipg", "per"; 721 #pwm-cells = <3>; 722 status = "disabled"; 723 }; 724 725 pwm2: pwm@30670000 { 726 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 727 reg = <0x30670000 0x10000>; 728 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 730 <&clks IMX7D_PWM2_ROOT_CLK>; 731 clock-names = "ipg", "per"; 732 #pwm-cells = <3>; 733 status = "disabled"; 734 }; 735 736 pwm3: pwm@30680000 { 737 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 738 reg = <0x30680000 0x10000>; 739 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 741 <&clks IMX7D_PWM3_ROOT_CLK>; 742 clock-names = "ipg", "per"; 743 #pwm-cells = <3>; 744 status = "disabled"; 745 }; 746 747 pwm4: pwm@30690000 { 748 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 749 reg = <0x30690000 0x10000>; 750 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 752 <&clks IMX7D_PWM4_ROOT_CLK>; 753 clock-names = "ipg", "per"; 754 #pwm-cells = <3>; 755 status = "disabled"; 756 }; 757 758 csi: csi@30710000 { 759 compatible = "fsl,imx7-csi"; 760 reg = <0x30710000 0x10000>; 761 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&clks IMX7D_CLK_DUMMY>, 763 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 764 <&clks IMX7D_CLK_DUMMY>; 765 clock-names = "axi", "mclk", "dcic"; 766 status = "disabled"; 767 768 port { 769 csi_from_csi_mux: endpoint { 770 remote-endpoint = <&csi_mux_to_csi>; 771 }; 772 }; 773 }; 774 775 lcdif: lcdif@30730000 { 776 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; 777 reg = <0x30730000 0x10000>; 778 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 780 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 781 clock-names = "pix", "axi"; 782 status = "disabled"; 783 }; 784 785 mipi_csi: mipi-csi@30750000 { 786 compatible = "fsl,imx7-mipi-csi2"; 787 reg = <0x30750000 0x10000>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 792 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 793 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 794 clock-names = "pclk", "wrap", "phy"; 795 power-domains = <&pgc_mipi_phy>; 796 phy-supply = <®_1p0d>; 797 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 798 reset-names = "mrst"; 799 status = "disabled"; 800 801 port@0 { 802 reg = <0>; 803 }; 804 805 port@1 { 806 reg = <1>; 807 808 mipi_vc0_to_csi_mux: endpoint { 809 remote-endpoint = <&csi_mux_from_mipi_vc0>; 810 }; 811 }; 812 }; 813 }; 814 815 aips3: bus@30800000 { 816 compatible = "fsl,aips-bus", "simple-bus"; 817 #address-cells = <1>; 818 #size-cells = <1>; 819 reg = <0x30800000 0x400000>; 820 ranges; 821 822 spba-bus@30800000 { 823 compatible = "fsl,spba-bus", "simple-bus"; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 reg = <0x30800000 0x100000>; 827 ranges; 828 829 ecspi1: spi@30820000 { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 833 reg = <0x30820000 0x10000>; 834 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 836 <&clks IMX7D_ECSPI1_ROOT_CLK>; 837 clock-names = "ipg", "per"; 838 status = "disabled"; 839 }; 840 841 ecspi2: spi@30830000 { 842 #address-cells = <1>; 843 #size-cells = <0>; 844 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 845 reg = <0x30830000 0x10000>; 846 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 848 <&clks IMX7D_ECSPI2_ROOT_CLK>; 849 clock-names = "ipg", "per"; 850 status = "disabled"; 851 }; 852 853 ecspi3: spi@30840000 { 854 #address-cells = <1>; 855 #size-cells = <0>; 856 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 857 reg = <0x30840000 0x10000>; 858 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 860 <&clks IMX7D_ECSPI3_ROOT_CLK>; 861 clock-names = "ipg", "per"; 862 status = "disabled"; 863 }; 864 865 uart1: serial@30860000 { 866 compatible = "fsl,imx7d-uart", 867 "fsl,imx6q-uart"; 868 reg = <0x30860000 0x10000>; 869 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 871 <&clks IMX7D_UART1_ROOT_CLK>; 872 clock-names = "ipg", "per"; 873 status = "disabled"; 874 }; 875 876 uart2: serial@30890000 { 877 compatible = "fsl,imx7d-uart", 878 "fsl,imx6q-uart"; 879 reg = <0x30890000 0x10000>; 880 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 882 <&clks IMX7D_UART2_ROOT_CLK>; 883 clock-names = "ipg", "per"; 884 status = "disabled"; 885 }; 886 887 uart3: serial@30880000 { 888 compatible = "fsl,imx7d-uart", 889 "fsl,imx6q-uart"; 890 reg = <0x30880000 0x10000>; 891 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 893 <&clks IMX7D_UART3_ROOT_CLK>; 894 clock-names = "ipg", "per"; 895 status = "disabled"; 896 }; 897 898 sai1: sai@308a0000 { 899 #sound-dai-cells = <0>; 900 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 901 reg = <0x308a0000 0x10000>; 902 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 904 <&clks IMX7D_SAI1_ROOT_CLK>, 905 <&clks IMX7D_CLK_DUMMY>, 906 <&clks IMX7D_CLK_DUMMY>; 907 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 908 dma-names = "rx", "tx"; 909 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 910 status = "disabled"; 911 }; 912 913 sai2: sai@308b0000 { 914 #sound-dai-cells = <0>; 915 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 916 reg = <0x308b0000 0x10000>; 917 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 919 <&clks IMX7D_SAI2_ROOT_CLK>, 920 <&clks IMX7D_CLK_DUMMY>, 921 <&clks IMX7D_CLK_DUMMY>; 922 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 923 dma-names = "rx", "tx"; 924 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 925 status = "disabled"; 926 }; 927 928 sai3: sai@308c0000 { 929 #sound-dai-cells = <0>; 930 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 931 reg = <0x308c0000 0x10000>; 932 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 934 <&clks IMX7D_SAI3_ROOT_CLK>, 935 <&clks IMX7D_CLK_DUMMY>, 936 <&clks IMX7D_CLK_DUMMY>; 937 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 938 dma-names = "rx", "tx"; 939 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 940 status = "disabled"; 941 }; 942 }; 943 944 crypto: crypto@30900000 { 945 compatible = "fsl,sec-v4.0"; 946 #address-cells = <1>; 947 #size-cells = <1>; 948 reg = <0x30900000 0x40000>; 949 ranges = <0 0x30900000 0x40000>; 950 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clks IMX7D_CAAM_CLK>, 952 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 953 clock-names = "ipg", "aclk"; 954 955 sec_jr0: jr@1000 { 956 compatible = "fsl,sec-v4.0-job-ring"; 957 reg = <0x1000 0x1000>; 958 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 959 }; 960 961 sec_jr1: jr@2000 { 962 compatible = "fsl,sec-v4.0-job-ring"; 963 reg = <0x2000 0x1000>; 964 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 965 }; 966 967 sec_jr2: jr@3000 { 968 compatible = "fsl,sec-v4.0-job-ring"; 969 reg = <0x3000 0x1000>; 970 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 971 }; 972 }; 973 974 flexcan1: can@30a00000 { 975 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 976 reg = <0x30a00000 0x10000>; 977 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clks IMX7D_CLK_DUMMY>, 979 <&clks IMX7D_CAN1_ROOT_CLK>; 980 clock-names = "ipg", "per"; 981 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 982 status = "disabled"; 983 }; 984 985 flexcan2: can@30a10000 { 986 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 987 reg = <0x30a10000 0x10000>; 988 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&clks IMX7D_CLK_DUMMY>, 990 <&clks IMX7D_CAN2_ROOT_CLK>; 991 clock-names = "ipg", "per"; 992 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 993 status = "disabled"; 994 }; 995 996 i2c1: i2c@30a20000 { 997 #address-cells = <1>; 998 #size-cells = <0>; 999 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1000 reg = <0x30a20000 0x10000>; 1001 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 1003 status = "disabled"; 1004 }; 1005 1006 i2c2: i2c@30a30000 { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1010 reg = <0x30a30000 0x10000>; 1011 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c3: i2c@30a40000 { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1020 reg = <0x30a40000 0x10000>; 1021 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1023 status = "disabled"; 1024 }; 1025 1026 i2c4: i2c@30a50000 { 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1030 reg = <0x30a50000 0x10000>; 1031 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1033 status = "disabled"; 1034 }; 1035 1036 uart4: serial@30a60000 { 1037 compatible = "fsl,imx7d-uart", 1038 "fsl,imx6q-uart"; 1039 reg = <0x30a60000 0x10000>; 1040 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1042 <&clks IMX7D_UART4_ROOT_CLK>; 1043 clock-names = "ipg", "per"; 1044 status = "disabled"; 1045 }; 1046 1047 uart5: serial@30a70000 { 1048 compatible = "fsl,imx7d-uart", 1049 "fsl,imx6q-uart"; 1050 reg = <0x30a70000 0x10000>; 1051 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1053 <&clks IMX7D_UART5_ROOT_CLK>; 1054 clock-names = "ipg", "per"; 1055 status = "disabled"; 1056 }; 1057 1058 uart6: serial@30a80000 { 1059 compatible = "fsl,imx7d-uart", 1060 "fsl,imx6q-uart"; 1061 reg = <0x30a80000 0x10000>; 1062 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1064 <&clks IMX7D_UART6_ROOT_CLK>; 1065 clock-names = "ipg", "per"; 1066 status = "disabled"; 1067 }; 1068 1069 uart7: serial@30a90000 { 1070 compatible = "fsl,imx7d-uart", 1071 "fsl,imx6q-uart"; 1072 reg = <0x30a90000 0x10000>; 1073 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1075 <&clks IMX7D_UART7_ROOT_CLK>; 1076 clock-names = "ipg", "per"; 1077 status = "disabled"; 1078 }; 1079 1080 mu0a: mailbox@30aa0000 { 1081 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1082 reg = <0x30aa0000 0x10000>; 1083 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1085 #mbox-cells = <2>; 1086 status = "disabled"; 1087 }; 1088 1089 mu0b: mailbox@30ab0000 { 1090 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1091 reg = <0x30ab0000 0x10000>; 1092 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1094 #mbox-cells = <2>; 1095 fsl,mu-side-b; 1096 status = "disabled"; 1097 }; 1098 1099 usbotg1: usb@30b10000 { 1100 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1101 reg = <0x30b10000 0x200>; 1102 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1104 fsl,usbphy = <&usbphynop1>; 1105 fsl,usbmisc = <&usbmisc1 0>; 1106 phy-clkgate-delay-us = <400>; 1107 status = "disabled"; 1108 }; 1109 1110 usbh: usb@30b30000 { 1111 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1112 reg = <0x30b30000 0x200>; 1113 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1115 fsl,usbphy = <&usbphynop3>; 1116 fsl,usbmisc = <&usbmisc3 0>; 1117 phy_type = "hsic"; 1118 dr_mode = "host"; 1119 phy-clkgate-delay-us = <400>; 1120 status = "disabled"; 1121 }; 1122 1123 usbmisc1: usbmisc@30b10200 { 1124 #index-cells = <1>; 1125 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1126 reg = <0x30b10200 0x200>; 1127 }; 1128 1129 usbmisc3: usbmisc@30b30200 { 1130 #index-cells = <1>; 1131 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1132 reg = <0x30b30200 0x200>; 1133 }; 1134 1135 usdhc1: mmc@30b40000 { 1136 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1137 reg = <0x30b40000 0x10000>; 1138 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1140 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1141 <&clks IMX7D_USDHC1_ROOT_CLK>; 1142 clock-names = "ipg", "ahb", "per"; 1143 bus-width = <4>; 1144 fsl,tuning-step = <2>; 1145 fsl,tuning-start-tap = <20>; 1146 status = "disabled"; 1147 }; 1148 1149 usdhc2: mmc@30b50000 { 1150 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1151 reg = <0x30b50000 0x10000>; 1152 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1154 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1155 <&clks IMX7D_USDHC2_ROOT_CLK>; 1156 clock-names = "ipg", "ahb", "per"; 1157 bus-width = <4>; 1158 fsl,tuning-step = <2>; 1159 fsl,tuning-start-tap = <20>; 1160 status = "disabled"; 1161 }; 1162 1163 usdhc3: mmc@30b60000 { 1164 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1165 reg = <0x30b60000 0x10000>; 1166 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1168 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1169 <&clks IMX7D_USDHC3_ROOT_CLK>; 1170 clock-names = "ipg", "ahb", "per"; 1171 bus-width = <4>; 1172 fsl,tuning-step = <2>; 1173 fsl,tuning-start-tap = <20>; 1174 status = "disabled"; 1175 }; 1176 1177 qspi: spi@30bb0000 { 1178 compatible = "fsl,imx7d-qspi"; 1179 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1180 reg-names = "QuadSPI", "QuadSPI-memory"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1185 <&clks IMX7D_QSPI_ROOT_CLK>; 1186 clock-names = "qspi_en", "qspi"; 1187 status = "disabled"; 1188 }; 1189 1190 sdma: dma-controller@30bd0000 { 1191 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1192 reg = <0x30bd0000 0x10000>; 1193 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1195 <&clks IMX7D_SDMA_CORE_CLK>; 1196 clock-names = "ipg", "ahb"; 1197 #dma-cells = <3>; 1198 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1199 }; 1200 1201 fec1: ethernet@30be0000 { 1202 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1203 reg = <0x30be0000 0x10000>; 1204 interrupt-names = "int0", "int1", "int2", "pps"; 1205 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1210 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1211 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1212 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1213 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1214 clock-names = "ipg", "ahb", "ptp", 1215 "enet_clk_ref", "enet_out"; 1216 fsl,num-tx-queues = <3>; 1217 fsl,num-rx-queues = <3>; 1218 fsl,stop-mode = <&gpr 0x10 3>; 1219 status = "disabled"; 1220 }; 1221 }; 1222 1223 dma_apbh: dma-controller@33000000 { 1224 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1225 reg = <0x33000000 0x2000>; 1226 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1230 #dma-cells = <1>; 1231 dma-channels = <4>; 1232 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1233 }; 1234 1235 gpmi: nand-controller@33002000{ 1236 compatible = "fsl,imx7d-gpmi-nand"; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1240 reg-names = "gpmi-nand", "bch"; 1241 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1242 interrupt-names = "bch"; 1243 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1244 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1245 clock-names = "gpmi_io", "gpmi_bch_apb"; 1246 dmas = <&dma_apbh 0>; 1247 dma-names = "rx-tx"; 1248 status = "disabled"; 1249 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1250 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1251 }; 1252 }; 1253}; 1254