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1  /*
2   * arch/arm/mach-omap2/control.h
3   *
4   * OMAP2/3/4 System Control Module definitions
5   *
6   * Copyright (C) 2007-2010 Texas Instruments, Inc.
7   * Copyright (C) 2007-2008, 2010 Nokia Corporation
8   *
9   * Written by Paul Walmsley
10   *
11   * This program is free software; you can redistribute it and/or modify
12   * it under the terms of the GNU General Public License as published by
13   * the Free Software Foundation.
14   */
15  
16  #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
17  #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
18  
19  #include "am33xx.h"
20  
21  #ifndef __ASSEMBLY__
22  #define OMAP242X_CTRL_REGADDR(reg)					\
23  		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24  #define OMAP243X_CTRL_REGADDR(reg)					\
25  		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26  #define OMAP343X_CTRL_REGADDR(reg)					\
27  		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28  #define AM33XX_CTRL_REGADDR(reg)					\
29  		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
30  #else
31  #define OMAP242X_CTRL_REGADDR(reg)					\
32  		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
33  #define OMAP243X_CTRL_REGADDR(reg)					\
34  		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
35  #define OMAP343X_CTRL_REGADDR(reg)					\
36  		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
37  #define AM33XX_CTRL_REGADDR(reg)					\
38  		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
39  #endif /* __ASSEMBLY__ */
40  
41  /*
42   * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
43   * OMAP24XX and OMAP34XX.
44   */
45  
46  /* Control submodule offsets */
47  
48  #define OMAP2_CONTROL_INTERFACE		0x000
49  #define OMAP2_CONTROL_PADCONFS		0x030
50  #define OMAP2_CONTROL_GENERAL		0x270
51  #define OMAP343X_CONTROL_MEM_WKUP	0x600
52  #define OMAP343X_CONTROL_PADCONFS_WKUP	0xa00
53  #define OMAP343X_CONTROL_GENERAL_WKUP	0xa60
54  
55  /* TI81XX spefic control submodules */
56  #define TI81XX_CONTROL_DEVBOOT		0x040
57  #define TI81XX_CONTROL_DEVCONF		0x600
58  
59  /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
60  
61  #define OMAP2_CONTROL_SYSCONFIG		(OMAP2_CONTROL_INTERFACE + 0x10)
62  
63  /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
64  #define OMAP2_CONTROL_DEVCONF0		(OMAP2_CONTROL_GENERAL + 0x0004)
65  #define OMAP2_CONTROL_MSUSPENDMUX_0	(OMAP2_CONTROL_GENERAL + 0x0020)
66  #define OMAP2_CONTROL_MSUSPENDMUX_1	(OMAP2_CONTROL_GENERAL + 0x0024)
67  #define OMAP2_CONTROL_MSUSPENDMUX_2	(OMAP2_CONTROL_GENERAL + 0x0028)
68  #define OMAP2_CONTROL_MSUSPENDMUX_3	(OMAP2_CONTROL_GENERAL + 0x002c)
69  #define OMAP2_CONTROL_MSUSPENDMUX_4	(OMAP2_CONTROL_GENERAL + 0x0030)
70  #define OMAP2_CONTROL_MSUSPENDMUX_5	(OMAP2_CONTROL_GENERAL + 0x0034)
71  #define OMAP2_CONTROL_SEC_CTRL		(OMAP2_CONTROL_GENERAL + 0x0040)
72  #define OMAP2_CONTROL_RPUB_KEY_H_0	(OMAP2_CONTROL_GENERAL + 0x0090)
73  #define OMAP2_CONTROL_RPUB_KEY_H_1	(OMAP2_CONTROL_GENERAL + 0x0094)
74  #define OMAP2_CONTROL_RPUB_KEY_H_2	(OMAP2_CONTROL_GENERAL + 0x0098)
75  #define OMAP2_CONTROL_RPUB_KEY_H_3	(OMAP2_CONTROL_GENERAL + 0x009c)
76  
77  /* 242x-only CONTROL_GENERAL register offsets */
78  #define OMAP242X_CONTROL_DEVCONF	OMAP2_CONTROL_DEVCONF0 /* match TRM */
79  #define OMAP242X_CONTROL_OCM_RAM_PERM	(OMAP2_CONTROL_GENERAL + 0x0068)
80  
81  /* 243x-only CONTROL_GENERAL register offsets */
82  /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
83  #define OMAP243X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0078)
84  #define OMAP243X_CONTROL_CSIRXFE	(OMAP2_CONTROL_GENERAL + 0x007c)
85  #define OMAP243X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
86  #define OMAP243X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
87  #define OMAP243X_CONTROL_IVA2_GEMCFG	(OMAP2_CONTROL_GENERAL + 0x0198)
88  #define OMAP243X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x0230)
89  
90  /* 24xx-only CONTROL_GENERAL register offsets */
91  #define OMAP24XX_CONTROL_DEBOBS		(OMAP2_CONTROL_GENERAL + 0x0000)
92  #define OMAP24XX_CONTROL_EMU_SUPPORT	(OMAP2_CONTROL_GENERAL + 0x0008)
93  #define OMAP24XX_CONTROL_SEC_TEST	(OMAP2_CONTROL_GENERAL + 0x0044)
94  #define OMAP24XX_CONTROL_PSA_CTRL	(OMAP2_CONTROL_GENERAL + 0x0048)
95  #define OMAP24XX_CONTROL_PSA_CMD	(OMAP2_CONTROL_GENERAL + 0x004c)
96  #define OMAP24XX_CONTROL_PSA_VALUE	(OMAP2_CONTROL_GENERAL + 0x0050)
97  #define OMAP24XX_CONTROL_SEC_EMU	(OMAP2_CONTROL_GENERAL + 0x0060)
98  #define OMAP24XX_CONTROL_SEC_TAP	(OMAP2_CONTROL_GENERAL + 0x0064)
99  #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD	(OMAP2_CONTROL_GENERAL + 0x006c)
100  #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD	(OMAP2_CONTROL_GENERAL + 0x0070)
101  #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD	(OMAP2_CONTROL_GENERAL + 0x0074)
102  #define OMAP24XX_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0080)
103  #define OMAP24XX_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0084)
104  #define OMAP24XX_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0088)
105  #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x008c)
106  #define OMAP24XX_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a0)
107  #define OMAP24XX_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00a4)
108  #define OMAP24XX_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00a8)
109  #define OMAP24XX_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00ac)
110  #define OMAP24XX_CONTROL_CUST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00b0)
111  #define OMAP24XX_CONTROL_CUST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00b4)
112  #define OMAP24XX_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c0)
113  #define OMAP24XX_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00c4)
114  #define OMAP24XX_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00c8)
115  #define OMAP24XX_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00cc)
116  #define OMAP24XX_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d0)
117  #define OMAP24XX_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00d4)
118  #define OMAP24XX_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00d8)
119  #define OMAP24XX_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00dc)
120  #define OMAP24XX_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e0)
121  #define OMAP24XX_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00e4)
122  
123  #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
124  
125  /* 34xx-only CONTROL_GENERAL register offsets */
126  #define OMAP343X_CONTROL_PADCONF_OFF	(OMAP2_CONTROL_GENERAL + 0x0000)
127  #define OMAP343X_CONTROL_MEM_DFTRW0	(OMAP2_CONTROL_GENERAL + 0x0008)
128  #define OMAP343X_CONTROL_MEM_DFTRW1	(OMAP2_CONTROL_GENERAL + 0x000c)
129  #define OMAP343X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0068)
130  #define OMAP343X_CONTROL_CSIRXFE		(OMAP2_CONTROL_GENERAL + 0x006c)
131  #define OMAP343X_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0070)
132  #define OMAP343X_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0074)
133  #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG	(OMAP2_CONTROL_GENERAL + 0x0078)
134  #define OMAP343X_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0080)
135  #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x0084)
136  #define OMAP343X_CONTROL_RPUB_KEY_H_4	(OMAP2_CONTROL_GENERAL + 0x00a0)
137  #define OMAP343X_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a8)
138  #define OMAP343X_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00ac)
139  #define OMAP343X_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00b0)
140  #define OMAP343X_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00b4)
141  #define OMAP343X_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c8)
142  #define OMAP343X_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00cc)
143  #define OMAP343X_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00d0)
144  #define OMAP343X_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00d4)
145  #define OMAP343X_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d8)
146  #define OMAP343X_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00dc)
147  #define OMAP343X_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00e0)
148  #define OMAP343X_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00e4)
149  #define OMAP343X_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e8)
150  #define OMAP343X_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00ec)
151  #define OMAP343X_CONTROL_TEST_KEY_10	(OMAP2_CONTROL_GENERAL + 0x00f0)
152  #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
153  #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
154  #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
155  #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
156  #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
157  #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
158  #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
159  #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
160  #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
161  #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
162  #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
163  #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
164  #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
165  #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
166  #define OMAP343X_CONTROL_DEBOBS(i)	(OMAP2_CONTROL_GENERAL + 0x01B0 \
167  					+ ((i) >> 1) * 4 + (!((i) & 1)) * 2)
168  #define OMAP343X_CONTROL_PROG_IO0	(OMAP2_CONTROL_GENERAL + 0x01D4)
169  #define OMAP343X_CONTROL_PROG_IO1	(OMAP2_CONTROL_GENERAL + 0x01D8)
170  #define OMAP343X_CONTROL_DSS_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E0)
171  #define OMAP343X_CONTROL_CORE_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E4)
172  #define OMAP343X_CONTROL_PER_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E8)
173  #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01EC)
174  #define OMAP343X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x02B0)
175  #define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02B4)
176  #define OMAP343X_CONTROL_SRAMLDO4	(OMAP2_CONTROL_GENERAL + 0x02B8)
177  #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
178  #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
179  
180  /* OMAP3630 only CONTROL_GENERAL register offsets */
181  #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
182  #define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
183  #define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
184  #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
185  #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
186  #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
187  #define OMAP3630_CONTROL_CAMERA_PHY_CTRL	(OMAP2_CONTROL_GENERAL + 0x02f0)
188  
189  /* OMAP44xx control efuse offsets */
190  #define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
191  #define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
192  #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
193  #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
194  #define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
195  #define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
196  #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
197  #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
198  #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB	0x24C
199  #define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
200  #define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
201  #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV	0x25A
202  
203  /* AM35XX only CONTROL_GENERAL register offsets */
204  #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
205  #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
206  #define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
207  #define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
208  #define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
209  #define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
210  #define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
211  
212  /* 34xx PADCONF register offsets */
213  #define OMAP343X_PADCONF_ETK(i)		(OMAP2_CONTROL_PADCONFS + 0x5a8 + \
214  						(i)*2)
215  #define OMAP343X_PADCONF_ETK_CLK	OMAP343X_PADCONF_ETK(0)
216  #define OMAP343X_PADCONF_ETK_CTL	OMAP343X_PADCONF_ETK(1)
217  #define OMAP343X_PADCONF_ETK_D0		OMAP343X_PADCONF_ETK(2)
218  #define OMAP343X_PADCONF_ETK_D1		OMAP343X_PADCONF_ETK(3)
219  #define OMAP343X_PADCONF_ETK_D2		OMAP343X_PADCONF_ETK(4)
220  #define OMAP343X_PADCONF_ETK_D3		OMAP343X_PADCONF_ETK(5)
221  #define OMAP343X_PADCONF_ETK_D4		OMAP343X_PADCONF_ETK(6)
222  #define OMAP343X_PADCONF_ETK_D5		OMAP343X_PADCONF_ETK(7)
223  #define OMAP343X_PADCONF_ETK_D6		OMAP343X_PADCONF_ETK(8)
224  #define OMAP343X_PADCONF_ETK_D7		OMAP343X_PADCONF_ETK(9)
225  #define OMAP343X_PADCONF_ETK_D8		OMAP343X_PADCONF_ETK(10)
226  #define OMAP343X_PADCONF_ETK_D9		OMAP343X_PADCONF_ETK(11)
227  #define OMAP343X_PADCONF_ETK_D10	OMAP343X_PADCONF_ETK(12)
228  #define OMAP343X_PADCONF_ETK_D11	OMAP343X_PADCONF_ETK(13)
229  #define OMAP343X_PADCONF_ETK_D12	OMAP343X_PADCONF_ETK(14)
230  #define OMAP343X_PADCONF_ETK_D13	OMAP343X_PADCONF_ETK(15)
231  #define OMAP343X_PADCONF_ETK_D14	OMAP343X_PADCONF_ETK(16)
232  #define OMAP343X_PADCONF_ETK_D15	OMAP343X_PADCONF_ETK(17)
233  
234  /* 34xx GENERAL_WKUP register offsets */
235  #define OMAP34XX_CONTROL_WKUP_CTRL	(OMAP343X_CONTROL_GENERAL_WKUP - 0x4)
236  #define OMAP36XX_GPIO_IO_PWRDNZ		BIT(6)
237  
238  #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
239  						0x008 + (i))
240  #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
241  #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
242  #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
243  #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
244  #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
245  
246  /* 36xx-only RTA - Retention till Access control registers and bits */
247  #define OMAP36XX_CONTROL_MEM_RTA_CTRL	0x40C
248  #define OMAP36XX_RTA_DISABLE		0x0
249  
250  /* 34xx D2D idle-related pins, handled by PM core */
251  #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
252  #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
253  
254  /* TI81XX CONTROL_DEVBOOT register offsets */
255  #define TI81XX_CONTROL_STATUS		(TI81XX_CONTROL_DEVBOOT + 0x000)
256  
257  /* TI81XX CONTROL_DEVCONF register offsets */
258  #define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
259  
260  /* OMAP4 CONTROL MODULE */
261  #define OMAP4_CTRL_MODULE_PAD_WKUP			0x4a31e000
262  #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2	0x0604
263  #define OMAP4_CTRL_MODULE_CORE_STATUS			0x02c4
264  #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1	0x0218
265  #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR		0x0304
266  #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY	0x0618
267  #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX	0x0608
268  
269  /* OMAP4 CONTROL_DSIPHY */
270  #define OMAP4_DSI2_LANEENABLE_SHIFT			29
271  #define OMAP4_DSI2_LANEENABLE_MASK			(0x7 << 29)
272  #define OMAP4_DSI1_LANEENABLE_SHIFT			24
273  #define OMAP4_DSI1_LANEENABLE_MASK			(0x1f << 24)
274  #define OMAP4_DSI1_PIPD_SHIFT				19
275  #define OMAP4_DSI1_PIPD_MASK				(0x1f << 19)
276  #define OMAP4_DSI2_PIPD_SHIFT				14
277  #define OMAP4_DSI2_PIPD_MASK				(0x1f << 14)
278  
279  /* OMAP4 CONTROL_CAMERA_RX */
280  #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT		24
281  #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK		(0x1f << 24)
282  #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT		29
283  #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK		(0x3 << 29)
284  #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT		21
285  #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK		(1 << 21)
286  #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT		19
287  #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK		(0x3 << 19)
288  #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT		18
289  #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK		(1 << 18)
290  #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT		16
291  #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK		(0x3 << 16)
292  
293  /* OMAP54XX CONTROL STATUS register */
294  #define OMAP5XXX_CONTROL_STATUS                0x134
295  #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
296  
297  /* DRA7XX CONTROL CORE BOOTSTRAP */
298  #define DRA7_CTRL_CORE_BOOTSTRAP	0x6c4
299  #define DRA7_SPEEDSELECT_MASK		(0x3 << 8)
300  
301  /*
302   * REVISIT: This list of registers is not comprehensive - there are more
303   * that should be added.
304   */
305  
306  /*
307   * Control module register bit defines - these should eventually go into
308   * their own regbits file.  Some of these will be complicated, depending
309   * on the device type (general-purpose, emulator, test, secure, bad, other)
310   * and the security mode (secure, non-secure, don't care)
311   */
312  /* CONTROL_DEVCONF0 bits */
313  #define OMAP2_MMCSDIO1ADPCLKISEL	(1 << 24) /* MMC1 loop back clock */
314  #define OMAP24XX_USBSTANDBYCTRL		(1 << 15)
315  #define OMAP2_MCBSP2_CLKS_MASK		(1 << 6)
316  #define OMAP2_MCBSP1_FSR_MASK		(1 << 4)
317  #define OMAP2_MCBSP1_CLKR_MASK		(1 << 3)
318  #define OMAP2_MCBSP1_CLKS_MASK		(1 << 2)
319  
320  /* CONTROL_DEVCONF1 bits */
321  #define OMAP243X_MMC1_ACTIVE_OVERWRITE	(1 << 31)
322  #define OMAP2_MMCSDIO2ADPCLKISEL	(1 << 6) /* MMC2 loop back clock */
323  #define OMAP2_MCBSP5_CLKS_MASK		(1 << 4) /* > 242x */
324  #define OMAP2_MCBSP4_CLKS_MASK		(1 << 2) /* > 242x */
325  #define OMAP2_MCBSP3_CLKS_MASK		(1 << 0) /* > 242x */
326  
327  /* CONTROL_STATUS bits */
328  #define OMAP2_DEVICETYPE_MASK		(0x7 << 8)
329  #define OMAP2_SYSBOOT_5_MASK		(1 << 5)
330  #define OMAP2_SYSBOOT_4_MASK		(1 << 4)
331  #define OMAP2_SYSBOOT_3_MASK		(1 << 3)
332  #define OMAP2_SYSBOOT_2_MASK		(1 << 2)
333  #define OMAP2_SYSBOOT_1_MASK		(1 << 1)
334  #define OMAP2_SYSBOOT_0_MASK		(1 << 0)
335  
336  /* CONTROL_PBIAS_LITE bits */
337  #define OMAP343X_PBIASLITESUPPLY_HIGH1	(1 << 15)
338  #define OMAP343X_PBIASLITEVMODEERROR1	(1 << 11)
339  #define OMAP343X_PBIASSPEEDCTRL1	(1 << 10)
340  #define OMAP343X_PBIASLITEPWRDNZ1	(1 << 9)
341  #define OMAP343X_PBIASLITEVMODE1	(1 << 8)
342  #define OMAP343X_PBIASLITESUPPLY_HIGH0	(1 << 7)
343  #define OMAP343X_PBIASLITEVMODEERROR0	(1 << 3)
344  #define OMAP2_PBIASSPEEDCTRL0		(1 << 2)
345  #define OMAP2_PBIASLITEPWRDNZ0		(1 << 1)
346  #define OMAP2_PBIASLITEVMODE0		(1 << 0)
347  
348  /* CONTROL_PROG_IO1 bits */
349  #define OMAP3630_PRG_SDMMC1_SPEEDCTRL	(1 << 20)
350  
351  /* CONTROL_IVA2_BOOTMOD bits */
352  #define OMAP3_IVA2_BOOTMOD_SHIFT	0
353  #define OMAP3_IVA2_BOOTMOD_MASK		(0xf << 0)
354  #define OMAP3_IVA2_BOOTMOD_IDLE		(0x1 << 0)
355  
356  /* CONTROL_PADCONF_X bits */
357  #define OMAP3_PADCONF_WAKEUPEVENT0	(1 << 15)
358  #define OMAP3_PADCONF_WAKEUPENABLE0	(1 << 14)
359  
360  #define OMAP343X_SCRATCHPAD_ROM		(OMAP343X_CTRL_BASE + 0x860)
361  #define OMAP343X_SCRATCHPAD		(OMAP343X_CTRL_BASE + 0x910)
362  #define OMAP343X_SCRATCHPAD_ROM_OFFSET	0x19C
363  #define OMAP343X_SCRATCHPAD_REGADDR(reg)	OMAP2_L4_IO_ADDRESS(\
364  						OMAP343X_SCRATCHPAD + reg)
365  
366  /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
367  #define AM35XX_USBOTG_VBUSP_CLK_SHIFT	0
368  #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT	1
369  #define AM35XX_VPFE_VBUSP_CLK_SHIFT	2
370  #define AM35XX_HECC_VBUSP_CLK_SHIFT	3
371  #define AM35XX_USBOTG_FCLK_SHIFT	8
372  #define AM35XX_CPGMAC_FCLK_SHIFT	9
373  #define AM35XX_VPFE_FCLK_SHIFT		10
374  
375  /* AM35XX CONTROL_LVL_INTR_CLEAR bits */
376  #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR	BIT(0)
377  #define AM35XX_CPGMAC_C0_RX_PULSE_CLR	BIT(1)
378  #define AM35XX_CPGMAC_C0_RX_THRESH_CLR	BIT(2)
379  #define AM35XX_CPGMAC_C0_TX_PULSE_CLR	BIT(3)
380  #define AM35XX_USBOTGSS_INT_CLR		BIT(4)
381  #define AM35XX_VPFE_CCDC_VD0_INT_CLR	BIT(5)
382  #define AM35XX_VPFE_CCDC_VD1_INT_CLR	BIT(6)
383  #define AM35XX_VPFE_CCDC_VD2_INT_CLR	BIT(7)
384  
385  /* AM35XX CONTROL_IP_SW_RESET bits */
386  #define AM35XX_USBOTGSS_SW_RST		BIT(0)
387  #define AM35XX_CPGMACSS_SW_RST		BIT(1)
388  #define AM35XX_VPFE_VBUSP_SW_RST	BIT(2)
389  #define AM35XX_HECC_SW_RST		BIT(3)
390  #define AM35XX_VPFE_PCLK_SW_RST		BIT(4)
391  
392  /* AM33XX CONTROL_STATUS register */
393  #define AM33XX_CONTROL_STATUS		0x040
394  #define AM33XX_CONTROL_SEC_CLK_CTRL	0x1bc
395  
396  /* AM33XX CONTROL_STATUS bitfields (partial) */
397  #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT		22
398  #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
399  #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)
400  
401  /* AM33XX PWMSS Control register */
402  #define AM33XX_PWMSS_TBCLK_CLKCTRL			0x664
403  
404  /* AM33XX  PWMSS Control bitfields */
405  #define AM33XX_PWMSS0_TBCLKEN_SHIFT			0
406  #define AM33XX_PWMSS1_TBCLKEN_SHIFT			1
407  #define AM33XX_PWMSS2_TBCLKEN_SHIFT			2
408  
409  /* DEV Feature register to identify AM33XX features */
410  #define AM33XX_DEV_FEATURE		0x604
411  #define AM33XX_SGX_MASK			BIT(29)
412  
413  /* Additional AM33XX/AM43XX CONTROL registers */
414  #define AM33XX_CONTROL_SYSCONFIG_OFFSET			0x0010
415  #define AM33XX_CONTROL_STATUS_OFFSET			0x0040
416  #define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET		0x01e0
417  #define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET	0x041c
418  #define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET		0x0428
419  #define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET		0x042c
420  #define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET	0x0444
421  #define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET		0x0448
422  #define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET		0x044c
423  #define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET	0x0458
424  #define AM33XX_CONTROL_MOSC_CTRL_OFFSET			0x0468
425  #define AM33XX_CONTROL_RCOSC_CTRL_OFFSET		0x046c
426  #define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET		0x0470
427  #define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET		0x0534
428  #define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET		0x0608
429  #define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET		0x060c
430  #define AM33XX_CONTROL_MMU_CFG_OFFSET			0x0610
431  #define AM33XX_CONTROL_TPTC_CFG_OFFSET			0x0614
432  #define AM33XX_CONTROL_USB_CTRL0_OFFSET			0x0620
433  #define AM33XX_CONTROL_USB_CTRL1_OFFSET			0x0628
434  #define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET		0x0648
435  #define AM43XX_CONTROL_USB_CTRL2_OFFSET			0x064c
436  #define AM43XX_CONTROL_GMII_SEL_OFFSET			0x0650
437  #define AM43XX_CONTROL_MPUSS_CTRL_OFFSET		0x0654
438  #define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET	0x0658
439  #define AM43XX_CONTROL_PWMSS_CTRL_OFFSET		0x0664
440  #define AM33XX_CONTROL_MREQPRIO_0_OFFSET		0x0670
441  #define AM33XX_CONTROL_MREQPRIO_1_OFFSET		0x0674
442  #define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET		0x0690
443  #define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET		0x0694
444  #define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET		0x0698
445  #define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET		0x069c
446  #define AM33XX_CONTROL_SMRT_CTRL_OFFSET			0x06a0
447  #define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET	0x06a4
448  #define AM43XX_CONTROL_CQDETECT_STS_OFFSET		0x0e00
449  #define AM43XX_CONTROL_CQDETECT_STS2_OFFSET		0x0e08
450  #define AM43XX_CONTROL_VTP_CTRL_OFFSET			0x0e0c
451  #define AM33XX_CONTROL_VREF_CTRL_OFFSET			0x0e14
452  #define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET		0x0f90
453  #define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET		0x0f94
454  #define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET		0x0f98
455  #define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET	0x0f9c
456  #define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET	0x0fa0
457  #define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET	0x0fa4
458  #define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET	0x0fa8
459  #define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET	0x0fac
460  #define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET	0x0fb0
461  #define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET	0x0fb4
462  #define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET	0x0fb8
463  #define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET	0x0fbc
464  #define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET	0x0fc0
465  #define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET	0x0fc4
466  #define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET	0x0fc8
467  #define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET	0x0fcc
468  #define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET		0x0fd0
469  #define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET		0x0fd4
470  #define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET		0x0fd8
471  #define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET		0x0fdc
472  #define AM33XX_CONTROL_RESET_ISO_OFFSET			0x1000
473  
474  /* CONTROL OMAP STATUS register to identify OMAP3 features */
475  #define OMAP3_CONTROL_OMAP_STATUS	0x044c
476  
477  #define OMAP3_SGX_SHIFT			13
478  #define OMAP3_SGX_MASK			(3 << OMAP3_SGX_SHIFT)
479  #define		FEAT_SGX_FULL		0
480  #define		FEAT_SGX_HALF		1
481  #define		FEAT_SGX_NONE		2
482  
483  #define OMAP3_IVA_SHIFT			12
484  #define OMAP3_IVA_MASK			(1 << OMAP3_IVA_SHIFT)
485  #define		FEAT_IVA		0
486  #define		FEAT_IVA_NONE		1
487  
488  #define OMAP3_L2CACHE_SHIFT		10
489  #define OMAP3_L2CACHE_MASK		(3 << OMAP3_L2CACHE_SHIFT)
490  #define		FEAT_L2CACHE_NONE	0
491  #define		FEAT_L2CACHE_64KB	1
492  #define		FEAT_L2CACHE_128KB	2
493  #define		FEAT_L2CACHE_256KB	3
494  
495  #define OMAP3_ISP_SHIFT			5
496  #define OMAP3_ISP_MASK			(1 << OMAP3_ISP_SHIFT)
497  #define		FEAT_ISP		0
498  #define		FEAT_ISP_NONE		1
499  
500  #define OMAP3_NEON_SHIFT		4
501  #define OMAP3_NEON_MASK			(1 << OMAP3_NEON_SHIFT)
502  #define		FEAT_NEON		0
503  #define		FEAT_NEON_NONE		1
504  
505  
506  #ifndef __ASSEMBLY__
507  #ifdef CONFIG_ARCH_OMAP2PLUS
508  extern u8 omap_ctrl_readb(u16 offset);
509  extern u16 omap_ctrl_readw(u16 offset);
510  extern u32 omap_ctrl_readl(u16 offset);
511  extern void omap_ctrl_writeb(u8 val, u16 offset);
512  extern void omap_ctrl_writew(u16 val, u16 offset);
513  extern void omap_ctrl_writel(u32 val, u16 offset);
514  
515  extern void omap3_save_scratchpad_contents(void);
516  extern void omap3_clear_scratchpad_contents(void);
517  extern void omap3_restore(void);
518  extern void omap3_restore_es3(void);
519  extern void omap3_restore_3630(void);
520  extern u32 omap3_arm_context[128];
521  extern void omap3_control_save_context(void);
522  extern void omap3_control_restore_context(void);
523  extern void omap3_ctrl_write_boot_mode(u8 bootmode);
524  extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
525  extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
526  extern void omap3630_ctrl_disable_rta(void);
527  extern int omap3_ctrl_save_padconf(void);
528  void omap3_ctrl_init(void);
529  int omap2_control_base_init(void);
530  int omap_control_init(void);
531  void omap2_set_globals_control(void __iomem *ctrl);
532  void __init omap3_control_legacy_iomap_init(void);
533  #else
534  #define omap_ctrl_readb(x)		0
535  #define omap_ctrl_readw(x)		0
536  #define omap_ctrl_readl(x)		0
537  #define omap4_ctrl_pad_readl(x)		0
538  #define omap_ctrl_writeb(x, y)		WARN_ON(1)
539  #define omap_ctrl_writew(x, y)		WARN_ON(1)
540  #define omap_ctrl_writel(x, y)		WARN_ON(1)
541  #define omap4_ctrl_pad_writel(x, y)	WARN_ON(1)
542  #endif
543  #endif	/* __ASSEMBLY__ */
544  
545  #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
546  
547