1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MSR_INDEX_H 3 #define _ASM_X86_MSR_INDEX_H 4 5 #include <linux/bits.h> 6 7 /* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14 /* x86-64 specific MSRs */ 15 #define MSR_EFER 0xc0000080 /* extended feature register */ 16 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25 /* EFER bits: */ 26 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27 #define _EFER_LME 8 /* Long mode enable */ 28 #define _EFER_LMA 10 /* Long mode active (read-only) */ 29 #define _EFER_NX 11 /* No execute enable */ 30 #define _EFER_SVME 12 /* Enable virtualization */ 31 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34 #define EFER_SCE (1<<_EFER_SCE) 35 #define EFER_LME (1<<_EFER_LME) 36 #define EFER_LMA (1<<_EFER_LMA) 37 #define EFER_NX (1<<_EFER_NX) 38 #define EFER_SVME (1<<_EFER_SVME) 39 #define EFER_LMSLE (1<<_EFER_LMSLE) 40 #define EFER_FFXSR (1<<_EFER_FFXSR) 41 42 /* Intel MSRs. Some also available on other CPUs */ 43 44 #define MSR_TEST_CTRL 0x00000033 45 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50 #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52 #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 55 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 56 57 /* A mask for bits which the kernel toggles when controlling mitigations */ 58 #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 59 | SPEC_CTRL_RRSBA_DIS_S) 60 61 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 62 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 63 #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ 64 65 #define MSR_PPIN_CTL 0x0000004e 66 #define MSR_PPIN 0x0000004f 67 68 #define MSR_IA32_PERFCTR0 0x000000c1 69 #define MSR_IA32_PERFCTR1 0x000000c2 70 #define MSR_FSB_FREQ 0x000000cd 71 #define MSR_PLATFORM_INFO 0x000000ce 72 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 73 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 74 75 #define MSR_IA32_UMWAIT_CONTROL 0xe1 76 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 77 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 78 /* 79 * The time field is bit[31:2], but representing a 32bit value with 80 * bit[1:0] zero. 81 */ 82 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 83 84 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 85 #define MSR_IA32_CORE_CAPS 0x000000cf 86 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 87 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 88 89 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 90 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 91 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 92 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 93 #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 94 #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 95 96 #define MSR_MTRRcap 0x000000fe 97 98 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 99 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 100 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 101 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 102 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 103 #define ARCH_CAP_SSB_NO BIT(4) /* 104 * Not susceptible to Speculative Store Bypass 105 * attack, so no Speculative Store Bypass 106 * control required. 107 */ 108 #define ARCH_CAP_MDS_NO BIT(5) /* 109 * Not susceptible to 110 * Microarchitectural Data 111 * Sampling (MDS) vulnerabilities. 112 */ 113 #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 114 * The processor is not susceptible to a 115 * machine check error due to modifying the 116 * code page size along with either the 117 * physical address or cache type 118 * without TLB invalidation. 119 */ 120 #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 121 #define ARCH_CAP_TAA_NO BIT(8) /* 122 * Not susceptible to 123 * TSX Async Abort (TAA) vulnerabilities. 124 */ 125 #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 126 * Not susceptible to SBDR and SSDP 127 * variants of Processor MMIO stale data 128 * vulnerabilities. 129 */ 130 #define ARCH_CAP_FBSDP_NO BIT(14) /* 131 * Not susceptible to FBSDP variant of 132 * Processor MMIO stale data 133 * vulnerabilities. 134 */ 135 #define ARCH_CAP_PSDP_NO BIT(15) /* 136 * Not susceptible to PSDP variant of 137 * Processor MMIO stale data 138 * vulnerabilities. 139 */ 140 #define ARCH_CAP_FB_CLEAR BIT(17) /* 141 * VERW clears CPU fill buffer 142 * even on MDS_NO CPUs. 143 */ 144 #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 145 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 146 * bit available to control VERW 147 * behavior. 148 */ 149 #define ARCH_CAP_RRSBA BIT(19) /* 150 * Indicates RET may use predictors 151 * other than the RSB. With eIBRS 152 * enabled predictions in kernel mode 153 * are restricted to targets in 154 * kernel. 155 */ 156 #define ARCH_CAP_PBRSB_NO BIT(24) /* 157 * Not susceptible to Post-Barrier 158 * Return Stack Buffer Predictions. 159 */ 160 #define ARCH_CAP_GDS_CTRL BIT(25) /* 161 * CPU is vulnerable to Gather 162 * Data Sampling (GDS) and 163 * has controls for mitigation. 164 */ 165 #define ARCH_CAP_GDS_NO BIT(26) /* 166 * CPU is not vulnerable to Gather 167 * Data Sampling (GDS). 168 */ 169 170 #define MSR_IA32_FLUSH_CMD 0x0000010b 171 #define L1D_FLUSH BIT(0) /* 172 * Writeback and invalidate the 173 * L1 data cache. 174 */ 175 176 #define MSR_IA32_BBL_CR_CTL 0x00000119 177 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 178 179 #define MSR_IA32_TSX_CTRL 0x00000122 180 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 181 #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 182 183 /* SRBDS support */ 184 #define MSR_IA32_MCU_OPT_CTRL 0x00000123 185 #define RNGDS_MITG_DIS BIT(0) 186 #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 187 #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ 188 #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ 189 190 #define MSR_IA32_SYSENTER_CS 0x00000174 191 #define MSR_IA32_SYSENTER_ESP 0x00000175 192 #define MSR_IA32_SYSENTER_EIP 0x00000176 193 194 #define MSR_IA32_MCG_CAP 0x00000179 195 #define MSR_IA32_MCG_STATUS 0x0000017a 196 #define MSR_IA32_MCG_CTL 0x0000017b 197 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 198 199 #define MSR_OFFCORE_RSP_0 0x000001a6 200 #define MSR_OFFCORE_RSP_1 0x000001a7 201 #define MSR_TURBO_RATIO_LIMIT 0x000001ad 202 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 203 #define MSR_TURBO_RATIO_LIMIT2 0x000001af 204 205 #define MSR_LBR_SELECT 0x000001c8 206 #define MSR_LBR_TOS 0x000001c9 207 208 #define MSR_IA32_POWER_CTL 0x000001fc 209 #define MSR_IA32_POWER_CTL_BIT_EE 19 210 211 #define MSR_LBR_NHM_FROM 0x00000680 212 #define MSR_LBR_NHM_TO 0x000006c0 213 #define MSR_LBR_CORE_FROM 0x00000040 214 #define MSR_LBR_CORE_TO 0x00000060 215 216 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 217 #define LBR_INFO_MISPRED BIT_ULL(63) 218 #define LBR_INFO_IN_TX BIT_ULL(62) 219 #define LBR_INFO_ABORT BIT_ULL(61) 220 #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 221 #define LBR_INFO_CYCLES 0xffff 222 #define LBR_INFO_BR_TYPE_OFFSET 56 223 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 224 225 #define MSR_ARCH_LBR_CTL 0x000014ce 226 #define ARCH_LBR_CTL_LBREN BIT(0) 227 #define ARCH_LBR_CTL_CPL_OFFSET 1 228 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 229 #define ARCH_LBR_CTL_STACK_OFFSET 3 230 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 231 #define ARCH_LBR_CTL_FILTER_OFFSET 16 232 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 233 #define MSR_ARCH_LBR_DEPTH 0x000014cf 234 #define MSR_ARCH_LBR_FROM_0 0x00001500 235 #define MSR_ARCH_LBR_TO_0 0x00001600 236 #define MSR_ARCH_LBR_INFO_0 0x00001200 237 238 #define MSR_IA32_PEBS_ENABLE 0x000003f1 239 #define MSR_PEBS_DATA_CFG 0x000003f2 240 #define MSR_IA32_DS_AREA 0x00000600 241 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 242 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 243 244 #define MSR_IA32_RTIT_CTL 0x00000570 245 #define RTIT_CTL_TRACEEN BIT(0) 246 #define RTIT_CTL_CYCLEACC BIT(1) 247 #define RTIT_CTL_OS BIT(2) 248 #define RTIT_CTL_USR BIT(3) 249 #define RTIT_CTL_PWR_EVT_EN BIT(4) 250 #define RTIT_CTL_FUP_ON_PTW BIT(5) 251 #define RTIT_CTL_FABRIC_EN BIT(6) 252 #define RTIT_CTL_CR3EN BIT(7) 253 #define RTIT_CTL_TOPA BIT(8) 254 #define RTIT_CTL_MTC_EN BIT(9) 255 #define RTIT_CTL_TSC_EN BIT(10) 256 #define RTIT_CTL_DISRETC BIT(11) 257 #define RTIT_CTL_PTW_EN BIT(12) 258 #define RTIT_CTL_BRANCH_EN BIT(13) 259 #define RTIT_CTL_MTC_RANGE_OFFSET 14 260 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 261 #define RTIT_CTL_CYC_THRESH_OFFSET 19 262 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 263 #define RTIT_CTL_PSB_FREQ_OFFSET 24 264 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 265 #define RTIT_CTL_ADDR0_OFFSET 32 266 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 267 #define RTIT_CTL_ADDR1_OFFSET 36 268 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 269 #define RTIT_CTL_ADDR2_OFFSET 40 270 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 271 #define RTIT_CTL_ADDR3_OFFSET 44 272 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 273 #define MSR_IA32_RTIT_STATUS 0x00000571 274 #define RTIT_STATUS_FILTEREN BIT(0) 275 #define RTIT_STATUS_CONTEXTEN BIT(1) 276 #define RTIT_STATUS_TRIGGEREN BIT(2) 277 #define RTIT_STATUS_BUFFOVF BIT(3) 278 #define RTIT_STATUS_ERROR BIT(4) 279 #define RTIT_STATUS_STOPPED BIT(5) 280 #define RTIT_STATUS_BYTECNT_OFFSET 32 281 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 282 #define MSR_IA32_RTIT_ADDR0_A 0x00000580 283 #define MSR_IA32_RTIT_ADDR0_B 0x00000581 284 #define MSR_IA32_RTIT_ADDR1_A 0x00000582 285 #define MSR_IA32_RTIT_ADDR1_B 0x00000583 286 #define MSR_IA32_RTIT_ADDR2_A 0x00000584 287 #define MSR_IA32_RTIT_ADDR2_B 0x00000585 288 #define MSR_IA32_RTIT_ADDR3_A 0x00000586 289 #define MSR_IA32_RTIT_ADDR3_B 0x00000587 290 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 291 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 292 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 293 294 #define MSR_MTRRfix64K_00000 0x00000250 295 #define MSR_MTRRfix16K_80000 0x00000258 296 #define MSR_MTRRfix16K_A0000 0x00000259 297 #define MSR_MTRRfix4K_C0000 0x00000268 298 #define MSR_MTRRfix4K_C8000 0x00000269 299 #define MSR_MTRRfix4K_D0000 0x0000026a 300 #define MSR_MTRRfix4K_D8000 0x0000026b 301 #define MSR_MTRRfix4K_E0000 0x0000026c 302 #define MSR_MTRRfix4K_E8000 0x0000026d 303 #define MSR_MTRRfix4K_F0000 0x0000026e 304 #define MSR_MTRRfix4K_F8000 0x0000026f 305 #define MSR_MTRRdefType 0x000002ff 306 307 #define MSR_IA32_CR_PAT 0x00000277 308 309 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 310 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 311 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 312 #define MSR_IA32_LASTINTFROMIP 0x000001dd 313 #define MSR_IA32_LASTINTTOIP 0x000001de 314 315 #define MSR_IA32_PASID 0x00000d93 316 #define MSR_IA32_PASID_VALID BIT_ULL(31) 317 318 /* DEBUGCTLMSR bits (others vary by model): */ 319 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 320 #define DEBUGCTLMSR_BTF_SHIFT 1 321 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 322 #define DEBUGCTLMSR_TR (1UL << 6) 323 #define DEBUGCTLMSR_BTS (1UL << 7) 324 #define DEBUGCTLMSR_BTINT (1UL << 8) 325 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 326 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 327 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 328 #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 329 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 330 #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 331 332 #define MSR_PEBS_FRONTEND 0x000003f7 333 334 #define MSR_IA32_MC0_CTL 0x00000400 335 #define MSR_IA32_MC0_STATUS 0x00000401 336 #define MSR_IA32_MC0_ADDR 0x00000402 337 #define MSR_IA32_MC0_MISC 0x00000403 338 339 /* C-state Residency Counters */ 340 #define MSR_PKG_C3_RESIDENCY 0x000003f8 341 #define MSR_PKG_C6_RESIDENCY 0x000003f9 342 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 343 #define MSR_PKG_C7_RESIDENCY 0x000003fa 344 #define MSR_CORE_C3_RESIDENCY 0x000003fc 345 #define MSR_CORE_C6_RESIDENCY 0x000003fd 346 #define MSR_CORE_C7_RESIDENCY 0x000003fe 347 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 348 #define MSR_PKG_C2_RESIDENCY 0x0000060d 349 #define MSR_PKG_C8_RESIDENCY 0x00000630 350 #define MSR_PKG_C9_RESIDENCY 0x00000631 351 #define MSR_PKG_C10_RESIDENCY 0x00000632 352 353 /* Interrupt Response Limit */ 354 #define MSR_PKGC3_IRTL 0x0000060a 355 #define MSR_PKGC6_IRTL 0x0000060b 356 #define MSR_PKGC7_IRTL 0x0000060c 357 #define MSR_PKGC8_IRTL 0x00000633 358 #define MSR_PKGC9_IRTL 0x00000634 359 #define MSR_PKGC10_IRTL 0x00000635 360 361 /* Run Time Average Power Limiting (RAPL) Interface */ 362 363 #define MSR_RAPL_POWER_UNIT 0x00000606 364 365 #define MSR_PKG_POWER_LIMIT 0x00000610 366 #define MSR_PKG_ENERGY_STATUS 0x00000611 367 #define MSR_PKG_PERF_STATUS 0x00000613 368 #define MSR_PKG_POWER_INFO 0x00000614 369 370 #define MSR_DRAM_POWER_LIMIT 0x00000618 371 #define MSR_DRAM_ENERGY_STATUS 0x00000619 372 #define MSR_DRAM_PERF_STATUS 0x0000061b 373 #define MSR_DRAM_POWER_INFO 0x0000061c 374 375 #define MSR_PP0_POWER_LIMIT 0x00000638 376 #define MSR_PP0_ENERGY_STATUS 0x00000639 377 #define MSR_PP0_POLICY 0x0000063a 378 #define MSR_PP0_PERF_STATUS 0x0000063b 379 380 #define MSR_PP1_POWER_LIMIT 0x00000640 381 #define MSR_PP1_ENERGY_STATUS 0x00000641 382 #define MSR_PP1_POLICY 0x00000642 383 384 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 385 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 386 387 /* Config TDP MSRs */ 388 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 389 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 390 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 391 #define MSR_CONFIG_TDP_CONTROL 0x0000064B 392 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 393 394 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 395 396 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 397 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 398 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 399 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 400 401 #define MSR_CORE_C1_RES 0x00000660 402 #define MSR_MODULE_C6_RES_MS 0x00000664 403 404 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 405 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 406 407 #define MSR_ATOM_CORE_RATIOS 0x0000066a 408 #define MSR_ATOM_CORE_VIDS 0x0000066b 409 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 410 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 411 412 413 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 414 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 415 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 416 417 /* Hardware P state interface */ 418 #define MSR_PPERF 0x0000064e 419 #define MSR_PERF_LIMIT_REASONS 0x0000064f 420 #define MSR_PM_ENABLE 0x00000770 421 #define MSR_HWP_CAPABILITIES 0x00000771 422 #define MSR_HWP_REQUEST_PKG 0x00000772 423 #define MSR_HWP_INTERRUPT 0x00000773 424 #define MSR_HWP_REQUEST 0x00000774 425 #define MSR_HWP_STATUS 0x00000777 426 427 /* CPUID.6.EAX */ 428 #define HWP_BASE_BIT (1<<7) 429 #define HWP_NOTIFICATIONS_BIT (1<<8) 430 #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 431 #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 432 #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 433 434 /* IA32_HWP_CAPABILITIES */ 435 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 436 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 437 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 438 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 439 440 /* IA32_HWP_REQUEST */ 441 #define HWP_MIN_PERF(x) (x & 0xff) 442 #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 443 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 444 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 445 #define HWP_EPP_PERFORMANCE 0x00 446 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 447 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 448 #define HWP_EPP_POWERSAVE 0xFF 449 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 450 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 451 452 /* IA32_HWP_STATUS */ 453 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 454 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 455 456 /* IA32_HWP_INTERRUPT */ 457 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 458 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 459 460 #define MSR_AMD64_MC0_MASK 0xc0010044 461 462 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 463 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 464 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 465 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 466 467 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 468 469 /* These are consecutive and not in the normal 4er MCE bank block */ 470 #define MSR_IA32_MC0_CTL2 0x00000280 471 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 472 473 #define MSR_P6_PERFCTR0 0x000000c1 474 #define MSR_P6_PERFCTR1 0x000000c2 475 #define MSR_P6_EVNTSEL0 0x00000186 476 #define MSR_P6_EVNTSEL1 0x00000187 477 478 #define MSR_KNC_PERFCTR0 0x00000020 479 #define MSR_KNC_PERFCTR1 0x00000021 480 #define MSR_KNC_EVNTSEL0 0x00000028 481 #define MSR_KNC_EVNTSEL1 0x00000029 482 483 /* Alternative perfctr range with full access. */ 484 #define MSR_IA32_PMC0 0x000004c1 485 486 /* Auto-reload via MSR instead of DS area */ 487 #define MSR_RELOAD_PMC0 0x000014c1 488 #define MSR_RELOAD_FIXED_CTR0 0x00001309 489 490 /* 491 * AMD64 MSRs. Not complete. See the architecture manual for a more 492 * complete list. 493 */ 494 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 495 #define MSR_AMD64_TSC_RATIO 0xc0000104 496 #define MSR_AMD64_NB_CFG 0xc001001f 497 #define MSR_AMD64_PATCH_LOADER 0xc0010020 498 #define MSR_AMD_PERF_CTL 0xc0010062 499 #define MSR_AMD_PERF_STATUS 0xc0010063 500 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 501 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 502 #define MSR_AMD64_OSVW_STATUS 0xc0010141 503 #define MSR_AMD_PPIN_CTL 0xc00102f0 504 #define MSR_AMD_PPIN 0xc00102f1 505 #define MSR_AMD64_CPUID_FN_1 0xc0011004 506 #define MSR_AMD64_LS_CFG 0xc0011020 507 #define MSR_AMD64_DC_CFG 0xc0011022 508 #define MSR_AMD64_TW_CFG 0xc0011023 509 510 #define MSR_AMD64_DE_CFG 0xc0011029 511 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 512 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 513 #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 514 515 #define MSR_AMD64_BU_CFG2 0xc001102a 516 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 517 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 518 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 519 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 520 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 521 #define MSR_AMD64_IBSOPCTL 0xc0011033 522 #define MSR_AMD64_IBSOPRIP 0xc0011034 523 #define MSR_AMD64_IBSOPDATA 0xc0011035 524 #define MSR_AMD64_IBSOPDATA2 0xc0011036 525 #define MSR_AMD64_IBSOPDATA3 0xc0011037 526 #define MSR_AMD64_IBSDCLINAD 0xc0011038 527 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 528 #define MSR_AMD64_IBSOP_REG_COUNT 7 529 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 530 #define MSR_AMD64_IBSCTL 0xc001103a 531 #define MSR_AMD64_IBSBRTARGET 0xc001103b 532 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 533 #define MSR_AMD64_IBSOPDATA4 0xc001103d 534 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 535 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 536 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 537 #define MSR_AMD64_SEV 0xc0010131 538 #define MSR_AMD64_SEV_ENABLED_BIT 0 539 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 540 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 541 #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 542 543 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 544 545 /* Zen4 */ 546 #define MSR_ZEN4_BP_CFG 0xc001102e 547 #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 548 549 /* Zen 2 */ 550 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 551 #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 552 553 /* Fam 17h MSRs */ 554 #define MSR_F17H_IRPERF 0xc00000e9 555 556 /* Fam 16h MSRs */ 557 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 558 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 559 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 560 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 561 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 562 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 563 564 /* Fam 15h MSRs */ 565 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 566 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 567 #define MSR_F15H_PERF_CTL 0xc0010200 568 #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 569 #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 570 #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 571 #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 572 #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 573 #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 574 575 #define MSR_F15H_PERF_CTR 0xc0010201 576 #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 577 #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 578 #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 579 #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 580 #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 581 #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 582 583 #define MSR_F15H_NB_PERF_CTL 0xc0010240 584 #define MSR_F15H_NB_PERF_CTR 0xc0010241 585 #define MSR_F15H_PTSC 0xc0010280 586 #define MSR_F15H_IC_CFG 0xc0011021 587 #define MSR_F15H_EX_CFG 0xc001102c 588 589 /* Fam 10h MSRs */ 590 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 591 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 592 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 593 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 594 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 595 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 596 #define MSR_FAM10H_NODE_ID 0xc001100c 597 598 /* K8 MSRs */ 599 #define MSR_K8_TOP_MEM1 0xc001001a 600 #define MSR_K8_TOP_MEM2 0xc001001d 601 #define MSR_K8_SYSCFG 0xc0010010 602 #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 603 #define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 604 #define MSR_K8_INT_PENDING_MSG 0xc0010055 605 /* C1E active bits in int pending message */ 606 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 607 #define MSR_K8_TSEG_ADDR 0xc0010112 608 #define MSR_K8_TSEG_MASK 0xc0010113 609 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 610 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 611 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 612 613 /* K7 MSRs */ 614 #define MSR_K7_EVNTSEL0 0xc0010000 615 #define MSR_K7_PERFCTR0 0xc0010004 616 #define MSR_K7_EVNTSEL1 0xc0010001 617 #define MSR_K7_PERFCTR1 0xc0010005 618 #define MSR_K7_EVNTSEL2 0xc0010002 619 #define MSR_K7_PERFCTR2 0xc0010006 620 #define MSR_K7_EVNTSEL3 0xc0010003 621 #define MSR_K7_PERFCTR3 0xc0010007 622 #define MSR_K7_CLK_CTL 0xc001001b 623 #define MSR_K7_HWCR 0xc0010015 624 #define MSR_K7_HWCR_SMMLOCK_BIT 0 625 #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 626 #define MSR_K7_HWCR_IRPERF_EN_BIT 30 627 #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 628 #define MSR_K7_FID_VID_CTL 0xc0010041 629 #define MSR_K7_FID_VID_STATUS 0xc0010042 630 631 /* K6 MSRs */ 632 #define MSR_K6_WHCR 0xc0000082 633 #define MSR_K6_UWCCR 0xc0000085 634 #define MSR_K6_EPMR 0xc0000086 635 #define MSR_K6_PSOR 0xc0000087 636 #define MSR_K6_PFIR 0xc0000088 637 638 /* Centaur-Hauls/IDT defined MSRs. */ 639 #define MSR_IDT_FCR1 0x00000107 640 #define MSR_IDT_FCR2 0x00000108 641 #define MSR_IDT_FCR3 0x00000109 642 #define MSR_IDT_FCR4 0x0000010a 643 644 #define MSR_IDT_MCR0 0x00000110 645 #define MSR_IDT_MCR1 0x00000111 646 #define MSR_IDT_MCR2 0x00000112 647 #define MSR_IDT_MCR3 0x00000113 648 #define MSR_IDT_MCR4 0x00000114 649 #define MSR_IDT_MCR5 0x00000115 650 #define MSR_IDT_MCR6 0x00000116 651 #define MSR_IDT_MCR7 0x00000117 652 #define MSR_IDT_MCR_CTRL 0x00000120 653 654 /* VIA Cyrix defined MSRs*/ 655 #define MSR_VIA_FCR 0x00001107 656 #define MSR_VIA_LONGHAUL 0x0000110a 657 #define MSR_VIA_RNG 0x0000110b 658 #define MSR_VIA_BCR2 0x00001147 659 660 /* Transmeta defined MSRs */ 661 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 662 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 663 #define MSR_TMTA_LRTI_READOUT 0x80868018 664 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 665 666 /* Intel defined MSRs. */ 667 #define MSR_IA32_P5_MC_ADDR 0x00000000 668 #define MSR_IA32_P5_MC_TYPE 0x00000001 669 #define MSR_IA32_TSC 0x00000010 670 #define MSR_IA32_PLATFORM_ID 0x00000017 671 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 672 #define MSR_EBC_FREQUENCY_ID 0x0000002c 673 #define MSR_SMI_COUNT 0x00000034 674 675 /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 676 #define MSR_IA32_FEAT_CTL 0x0000003a 677 #define FEAT_CTL_LOCKED BIT(0) 678 #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 679 #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 680 #define FEAT_CTL_LMCE_ENABLED BIT(20) 681 682 #define MSR_IA32_TSC_ADJUST 0x0000003b 683 #define MSR_IA32_BNDCFGS 0x00000d90 684 685 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 686 687 #define MSR_IA32_XSS 0x00000da0 688 689 #define MSR_IA32_APICBASE 0x0000001b 690 #define MSR_IA32_APICBASE_BSP (1<<8) 691 #define MSR_IA32_APICBASE_ENABLE (1<<11) 692 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 693 694 #define MSR_IA32_TSCDEADLINE 0x000006e0 695 696 #define MSR_IA32_UCODE_WRITE 0x00000079 697 #define MSR_IA32_UCODE_REV 0x0000008b 698 699 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 700 #define MSR_IA32_SMBASE 0x0000009e 701 702 #define MSR_IA32_PERF_STATUS 0x00000198 703 #define MSR_IA32_PERF_CTL 0x00000199 704 #define INTEL_PERF_CTL_MASK 0xffff 705 706 #define MSR_IA32_MPERF 0x000000e7 707 #define MSR_IA32_APERF 0x000000e8 708 709 #define MSR_IA32_THERM_CONTROL 0x0000019a 710 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 711 712 #define THERM_INT_HIGH_ENABLE (1 << 0) 713 #define THERM_INT_LOW_ENABLE (1 << 1) 714 #define THERM_INT_PLN_ENABLE (1 << 24) 715 716 #define MSR_IA32_THERM_STATUS 0x0000019c 717 718 #define THERM_STATUS_PROCHOT (1 << 0) 719 #define THERM_STATUS_POWER_LIMIT (1 << 10) 720 721 #define MSR_THERM2_CTL 0x0000019d 722 723 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 724 725 #define MSR_IA32_MISC_ENABLE 0x000001a0 726 727 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 728 729 #define MSR_MISC_FEATURE_CONTROL 0x000001a4 730 #define MSR_MISC_PWR_MGMT 0x000001aa 731 732 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 733 #define ENERGY_PERF_BIAS_PERFORMANCE 0 734 #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 735 #define ENERGY_PERF_BIAS_NORMAL 6 736 #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 737 #define ENERGY_PERF_BIAS_POWERSAVE 15 738 739 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 740 741 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 742 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 743 744 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 745 746 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 747 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 748 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 749 750 /* Thermal Thresholds Support */ 751 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 752 #define THERM_SHIFT_THRESHOLD0 8 753 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 754 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 755 #define THERM_SHIFT_THRESHOLD1 16 756 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 757 #define THERM_STATUS_THRESHOLD0 (1 << 6) 758 #define THERM_LOG_THRESHOLD0 (1 << 7) 759 #define THERM_STATUS_THRESHOLD1 (1 << 8) 760 #define THERM_LOG_THRESHOLD1 (1 << 9) 761 762 /* MISC_ENABLE bits: architectural */ 763 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 764 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 765 #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 766 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 767 #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 768 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 769 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 770 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 771 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 772 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 773 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 774 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 775 #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 776 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 777 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 778 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 779 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 780 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 781 #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 782 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 783 784 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 785 #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 786 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 787 #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 788 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 789 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 790 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 791 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 792 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 793 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 794 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 795 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 796 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 797 #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 798 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 799 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 800 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 801 #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 802 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 803 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 804 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 805 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 806 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 807 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 808 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 809 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 810 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 811 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 812 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 813 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 814 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 815 816 /* MISC_FEATURES_ENABLES non-architectural features */ 817 #define MSR_MISC_FEATURES_ENABLES 0x00000140 818 819 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 820 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 821 #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 822 823 #define MSR_IA32_TSC_DEADLINE 0x000006E0 824 825 826 #define MSR_TSX_FORCE_ABORT 0x0000010F 827 828 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 829 #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 830 831 /* P4/Xeon+ specific */ 832 #define MSR_IA32_MCG_EAX 0x00000180 833 #define MSR_IA32_MCG_EBX 0x00000181 834 #define MSR_IA32_MCG_ECX 0x00000182 835 #define MSR_IA32_MCG_EDX 0x00000183 836 #define MSR_IA32_MCG_ESI 0x00000184 837 #define MSR_IA32_MCG_EDI 0x00000185 838 #define MSR_IA32_MCG_EBP 0x00000186 839 #define MSR_IA32_MCG_ESP 0x00000187 840 #define MSR_IA32_MCG_EFLAGS 0x00000188 841 #define MSR_IA32_MCG_EIP 0x00000189 842 #define MSR_IA32_MCG_RESERVED 0x0000018a 843 844 /* Pentium IV performance counter MSRs */ 845 #define MSR_P4_BPU_PERFCTR0 0x00000300 846 #define MSR_P4_BPU_PERFCTR1 0x00000301 847 #define MSR_P4_BPU_PERFCTR2 0x00000302 848 #define MSR_P4_BPU_PERFCTR3 0x00000303 849 #define MSR_P4_MS_PERFCTR0 0x00000304 850 #define MSR_P4_MS_PERFCTR1 0x00000305 851 #define MSR_P4_MS_PERFCTR2 0x00000306 852 #define MSR_P4_MS_PERFCTR3 0x00000307 853 #define MSR_P4_FLAME_PERFCTR0 0x00000308 854 #define MSR_P4_FLAME_PERFCTR1 0x00000309 855 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 856 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 857 #define MSR_P4_IQ_PERFCTR0 0x0000030c 858 #define MSR_P4_IQ_PERFCTR1 0x0000030d 859 #define MSR_P4_IQ_PERFCTR2 0x0000030e 860 #define MSR_P4_IQ_PERFCTR3 0x0000030f 861 #define MSR_P4_IQ_PERFCTR4 0x00000310 862 #define MSR_P4_IQ_PERFCTR5 0x00000311 863 #define MSR_P4_BPU_CCCR0 0x00000360 864 #define MSR_P4_BPU_CCCR1 0x00000361 865 #define MSR_P4_BPU_CCCR2 0x00000362 866 #define MSR_P4_BPU_CCCR3 0x00000363 867 #define MSR_P4_MS_CCCR0 0x00000364 868 #define MSR_P4_MS_CCCR1 0x00000365 869 #define MSR_P4_MS_CCCR2 0x00000366 870 #define MSR_P4_MS_CCCR3 0x00000367 871 #define MSR_P4_FLAME_CCCR0 0x00000368 872 #define MSR_P4_FLAME_CCCR1 0x00000369 873 #define MSR_P4_FLAME_CCCR2 0x0000036a 874 #define MSR_P4_FLAME_CCCR3 0x0000036b 875 #define MSR_P4_IQ_CCCR0 0x0000036c 876 #define MSR_P4_IQ_CCCR1 0x0000036d 877 #define MSR_P4_IQ_CCCR2 0x0000036e 878 #define MSR_P4_IQ_CCCR3 0x0000036f 879 #define MSR_P4_IQ_CCCR4 0x00000370 880 #define MSR_P4_IQ_CCCR5 0x00000371 881 #define MSR_P4_ALF_ESCR0 0x000003ca 882 #define MSR_P4_ALF_ESCR1 0x000003cb 883 #define MSR_P4_BPU_ESCR0 0x000003b2 884 #define MSR_P4_BPU_ESCR1 0x000003b3 885 #define MSR_P4_BSU_ESCR0 0x000003a0 886 #define MSR_P4_BSU_ESCR1 0x000003a1 887 #define MSR_P4_CRU_ESCR0 0x000003b8 888 #define MSR_P4_CRU_ESCR1 0x000003b9 889 #define MSR_P4_CRU_ESCR2 0x000003cc 890 #define MSR_P4_CRU_ESCR3 0x000003cd 891 #define MSR_P4_CRU_ESCR4 0x000003e0 892 #define MSR_P4_CRU_ESCR5 0x000003e1 893 #define MSR_P4_DAC_ESCR0 0x000003a8 894 #define MSR_P4_DAC_ESCR1 0x000003a9 895 #define MSR_P4_FIRM_ESCR0 0x000003a4 896 #define MSR_P4_FIRM_ESCR1 0x000003a5 897 #define MSR_P4_FLAME_ESCR0 0x000003a6 898 #define MSR_P4_FLAME_ESCR1 0x000003a7 899 #define MSR_P4_FSB_ESCR0 0x000003a2 900 #define MSR_P4_FSB_ESCR1 0x000003a3 901 #define MSR_P4_IQ_ESCR0 0x000003ba 902 #define MSR_P4_IQ_ESCR1 0x000003bb 903 #define MSR_P4_IS_ESCR0 0x000003b4 904 #define MSR_P4_IS_ESCR1 0x000003b5 905 #define MSR_P4_ITLB_ESCR0 0x000003b6 906 #define MSR_P4_ITLB_ESCR1 0x000003b7 907 #define MSR_P4_IX_ESCR0 0x000003c8 908 #define MSR_P4_IX_ESCR1 0x000003c9 909 #define MSR_P4_MOB_ESCR0 0x000003aa 910 #define MSR_P4_MOB_ESCR1 0x000003ab 911 #define MSR_P4_MS_ESCR0 0x000003c0 912 #define MSR_P4_MS_ESCR1 0x000003c1 913 #define MSR_P4_PMH_ESCR0 0x000003ac 914 #define MSR_P4_PMH_ESCR1 0x000003ad 915 #define MSR_P4_RAT_ESCR0 0x000003bc 916 #define MSR_P4_RAT_ESCR1 0x000003bd 917 #define MSR_P4_SAAT_ESCR0 0x000003ae 918 #define MSR_P4_SAAT_ESCR1 0x000003af 919 #define MSR_P4_SSU_ESCR0 0x000003be 920 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 921 922 #define MSR_P4_TBPU_ESCR0 0x000003c2 923 #define MSR_P4_TBPU_ESCR1 0x000003c3 924 #define MSR_P4_TC_ESCR0 0x000003c4 925 #define MSR_P4_TC_ESCR1 0x000003c5 926 #define MSR_P4_U2L_ESCR0 0x000003b0 927 #define MSR_P4_U2L_ESCR1 0x000003b1 928 929 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 930 931 /* Intel Core-based CPU performance counters */ 932 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 933 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 934 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 935 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 936 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 937 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 938 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 939 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 940 941 #define MSR_PERF_METRICS 0x00000329 942 943 /* PERF_GLOBAL_OVF_CTL bits */ 944 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 945 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 946 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 947 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 948 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 949 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 950 951 /* Geode defined MSRs */ 952 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 953 954 /* Intel VT MSRs */ 955 #define MSR_IA32_VMX_BASIC 0x00000480 956 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 957 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 958 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 959 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 960 #define MSR_IA32_VMX_MISC 0x00000485 961 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 962 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 963 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 964 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 965 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 966 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 967 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 968 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 969 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 970 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 971 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 972 #define MSR_IA32_VMX_VMFUNC 0x00000491 973 974 /* VMX_BASIC bits and bitmasks */ 975 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 976 #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 977 #define VMX_BASIC_64 0x0001000000000000LLU 978 #define VMX_BASIC_MEM_TYPE_SHIFT 50 979 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 980 #define VMX_BASIC_MEM_TYPE_WB 6LLU 981 #define VMX_BASIC_INOUT 0x0040000000000000LLU 982 983 /* MSR_IA32_VMX_MISC bits */ 984 #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 985 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 986 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 987 /* AMD-V MSRs */ 988 989 #define MSR_VM_CR 0xc0010114 990 #define MSR_VM_IGNNE 0xc0010115 991 #define MSR_VM_HSAVE_PA 0xc0010117 992 993 #endif /* _ASM_X86_MSR_INDEX_H */ 994