1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /** 3 * Copyright (C) ST-Ericsson SA 2010 4 * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson. 5 * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson. 6 * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson. 7 * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson. 8 * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson. 9 */ 10 11 #ifndef __CRYP_IRQP_H_ 12 #define __CRYP_IRQP_H_ 13 14 #include "cryp_irq.h" 15 16 /** 17 * 18 * CRYP Registers - Offset mapping 19 * +-----------------+ 20 * 00h | CRYP_CR | Configuration register 21 * +-----------------+ 22 * 04h | CRYP_SR | Status register 23 * +-----------------+ 24 * 08h | CRYP_DIN | Data In register 25 * +-----------------+ 26 * 0ch | CRYP_DOUT | Data out register 27 * +-----------------+ 28 * 10h | CRYP_DMACR | DMA control register 29 * +-----------------+ 30 * 14h | CRYP_IMSC | IMSC 31 * +-----------------+ 32 * 18h | CRYP_RIS | Raw interrupt status 33 * +-----------------+ 34 * 1ch | CRYP_MIS | Masked interrupt status. 35 * +-----------------+ 36 * Key registers 37 * IVR registers 38 * Peripheral 39 * Cell IDs 40 * 41 * Refer data structure for other register map 42 */ 43 44 /** 45 * struct cryp_register 46 * @cr - Configuration register 47 * @status - Status register 48 * @din - Data input register 49 * @din_size - Data input size register 50 * @dout - Data output register 51 * @dout_size - Data output size register 52 * @dmacr - Dma control register 53 * @imsc - Interrupt mask set/clear register 54 * @ris - Raw interrupt status 55 * @mis - Masked interrupt statu register 56 * @key_1_l - Key register 1 L 57 * @key_1_r - Key register 1 R 58 * @key_2_l - Key register 2 L 59 * @key_2_r - Key register 2 R 60 * @key_3_l - Key register 3 L 61 * @key_3_r - Key register 3 R 62 * @key_4_l - Key register 4 L 63 * @key_4_r - Key register 4 R 64 * @init_vect_0_l - init vector 0 L 65 * @init_vect_0_r - init vector 0 R 66 * @init_vect_1_l - init vector 1 L 67 * @init_vect_1_r - init vector 1 R 68 * @cryp_unused1 - unused registers 69 * @itcr - Integration test control register 70 * @itip - Integration test input register 71 * @itop - Integration test output register 72 * @cryp_unused2 - unused registers 73 * @periphId0 - FE0 CRYP Peripheral Identication Register 74 * @periphId1 - FE4 75 * @periphId2 - FE8 76 * @periphId3 - FEC 77 * @pcellId0 - FF0 CRYP PCell Identication Register 78 * @pcellId1 - FF4 79 * @pcellId2 - FF8 80 * @pcellId3 - FFC 81 */ 82 struct cryp_register { 83 u32 cr; /* Configuration register */ 84 u32 sr; /* Status register */ 85 u32 din; /* Data input register */ 86 u32 din_size; /* Data input size register */ 87 u32 dout; /* Data output register */ 88 u32 dout_size; /* Data output size register */ 89 u32 dmacr; /* Dma control register */ 90 u32 imsc; /* Interrupt mask set/clear register */ 91 u32 ris; /* Raw interrupt status */ 92 u32 mis; /* Masked interrupt statu register */ 93 94 u32 key_1_l; /*Key register 1 L */ 95 u32 key_1_r; /*Key register 1 R */ 96 u32 key_2_l; /*Key register 2 L */ 97 u32 key_2_r; /*Key register 2 R */ 98 u32 key_3_l; /*Key register 3 L */ 99 u32 key_3_r; /*Key register 3 R */ 100 u32 key_4_l; /*Key register 4 L */ 101 u32 key_4_r; /*Key register 4 R */ 102 103 u32 init_vect_0_l; /*init vector 0 L */ 104 u32 init_vect_0_r; /*init vector 0 R */ 105 u32 init_vect_1_l; /*init vector 1 L */ 106 u32 init_vect_1_r; /*init vector 1 R */ 107 108 u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)]; /* unused registers */ 109 u32 itcr; /*Integration test control register */ 110 u32 itip; /*Integration test input register */ 111 u32 itop; /*Integration test output register */ 112 u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)]; /* unused registers */ 113 114 u32 periphId0; /* FE0 CRYP Peripheral Identication Register */ 115 u32 periphId1; /* FE4 */ 116 u32 periphId2; /* FE8 */ 117 u32 periphId3; /* FEC */ 118 119 u32 pcellId0; /* FF0 CRYP PCell Identication Register */ 120 u32 pcellId1; /* FF4 */ 121 u32 pcellId2; /* FF8 */ 122 u32 pcellId3; /* FFC */ 123 }; 124 125 #endif 126