1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #ifdef pr_fmt
32 #undef pr_fmt
33 #endif
34
35 #define pr_fmt(fmt) "amdgpu: " fmt
36
37 #ifdef dev_fmt
38 #undef dev_fmt
39 #endif
40
41 #define dev_fmt(fmt) "amdgpu: " fmt
42
43 #include "amdgpu_ctx.h"
44
45 #include <linux/atomic.h>
46 #include <linux/wait.h>
47 #include <linux/list.h>
48 #include <linux/kref.h>
49 #include <linux/rbtree.h>
50 #include <linux/hashtable.h>
51 #include <linux/dma-fence.h>
52 #include <linux/pci.h>
53 #include <linux/aer.h>
54
55 #include <drm/ttm/ttm_bo_api.h>
56 #include <drm/ttm/ttm_bo_driver.h>
57 #include <drm/ttm/ttm_placement.h>
58 #include <drm/ttm/ttm_module.h>
59 #include <drm/ttm/ttm_execbuf_util.h>
60
61 #include <drm/amdgpu_drm.h>
62 #include <drm/drm_gem.h>
63 #include <drm/drm_ioctl.h>
64 #include <drm/gpu_scheduler.h>
65
66 #include <kgd_kfd_interface.h>
67 #include "dm_pp_interface.h"
68 #include "kgd_pp_interface.h"
69
70 #include "amd_shared.h"
71 #include "amdgpu_mode.h"
72 #include "amdgpu_ih.h"
73 #include "amdgpu_irq.h"
74 #include "amdgpu_ucode.h"
75 #include "amdgpu_ttm.h"
76 #include "amdgpu_psp.h"
77 #include "amdgpu_gds.h"
78 #include "amdgpu_sync.h"
79 #include "amdgpu_ring.h"
80 #include "amdgpu_vm.h"
81 #include "amdgpu_dpm.h"
82 #include "amdgpu_acp.h"
83 #include "amdgpu_uvd.h"
84 #include "amdgpu_vce.h"
85 #include "amdgpu_vcn.h"
86 #include "amdgpu_jpeg.h"
87 #include "amdgpu_mn.h"
88 #include "amdgpu_gmc.h"
89 #include "amdgpu_gfx.h"
90 #include "amdgpu_sdma.h"
91 #include "amdgpu_nbio.h"
92 #include "amdgpu_dm.h"
93 #include "amdgpu_virt.h"
94 #include "amdgpu_csa.h"
95 #include "amdgpu_gart.h"
96 #include "amdgpu_debugfs.h"
97 #include "amdgpu_job.h"
98 #include "amdgpu_bo_list.h"
99 #include "amdgpu_gem.h"
100 #include "amdgpu_doorbell.h"
101 #include "amdgpu_amdkfd.h"
102 #include "amdgpu_smu.h"
103 #include "amdgpu_discovery.h"
104 #include "amdgpu_mes.h"
105 #include "amdgpu_umc.h"
106 #include "amdgpu_mmhub.h"
107 #include "amdgpu_gfxhub.h"
108 #include "amdgpu_df.h"
109
110 #define MAX_GPU_INSTANCE 16
111
112 struct amdgpu_gpu_instance
113 {
114 struct amdgpu_device *adev;
115 int mgpu_fan_enabled;
116 };
117
118 struct amdgpu_mgpu_info
119 {
120 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
121 struct mutex mutex;
122 uint32_t num_gpu;
123 uint32_t num_dgpu;
124 uint32_t num_apu;
125 };
126
127 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
128
129 /*
130 * Modules parameters.
131 */
132 extern int amdgpu_modeset;
133 extern int amdgpu_vram_limit;
134 extern int amdgpu_vis_vram_limit;
135 extern int amdgpu_gart_size;
136 extern int amdgpu_gtt_size;
137 extern int amdgpu_moverate;
138 extern int amdgpu_benchmarking;
139 extern int amdgpu_testing;
140 extern int amdgpu_audio;
141 extern int amdgpu_disp_priority;
142 extern int amdgpu_hw_i2c;
143 extern int amdgpu_pcie_gen2;
144 extern int amdgpu_msi;
145 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
146 extern int amdgpu_dpm;
147 extern int amdgpu_fw_load_type;
148 extern int amdgpu_aspm;
149 extern int amdgpu_runtime_pm;
150 extern uint amdgpu_ip_block_mask;
151 extern int amdgpu_bapm;
152 extern int amdgpu_deep_color;
153 extern int amdgpu_vm_size;
154 extern int amdgpu_vm_block_size;
155 extern int amdgpu_vm_fragment_size;
156 extern int amdgpu_vm_fault_stop;
157 extern int amdgpu_vm_debug;
158 extern int amdgpu_vm_update_mode;
159 extern int amdgpu_exp_hw_support;
160 extern int amdgpu_dc;
161 extern int amdgpu_sched_jobs;
162 extern int amdgpu_sched_hw_submission;
163 extern uint amdgpu_pcie_gen_cap;
164 extern uint amdgpu_pcie_lane_cap;
165 extern uint amdgpu_cg_mask;
166 extern uint amdgpu_pg_mask;
167 extern uint amdgpu_sdma_phase_quantum;
168 extern char *amdgpu_disable_cu;
169 extern char *amdgpu_virtual_display;
170 extern uint amdgpu_pp_feature_mask;
171 extern uint amdgpu_force_long_training;
172 extern int amdgpu_job_hang_limit;
173 extern int amdgpu_lbpw;
174 extern int amdgpu_compute_multipipe;
175 extern int amdgpu_gpu_recovery;
176 extern int amdgpu_emu_mode;
177 extern uint amdgpu_smu_memory_pool_size;
178 extern uint amdgpu_dc_feature_mask;
179 extern uint amdgpu_dc_debug_mask;
180 extern uint amdgpu_dm_abm_level;
181 extern int amdgpu_backlight;
182 extern struct amdgpu_mgpu_info mgpu_info;
183 extern int amdgpu_ras_enable;
184 extern uint amdgpu_ras_mask;
185 extern int amdgpu_bad_page_threshold;
186 extern int amdgpu_async_gfx_ring;
187 extern int amdgpu_mcbp;
188 extern int amdgpu_discovery;
189 extern int amdgpu_mes;
190 extern int amdgpu_noretry;
191 extern int amdgpu_force_asic_type;
192 #ifdef CONFIG_HSA_AMD
193 extern int sched_policy;
194 extern bool debug_evictions;
195 extern bool no_system_mem_limit;
196 #else
197 static const int sched_policy = KFD_SCHED_POLICY_HWS;
198 static const bool debug_evictions; /* = false */
199 static const bool no_system_mem_limit;
200 #endif
201
202 extern int amdgpu_tmz;
203 extern int amdgpu_reset_method;
204
205 #ifdef CONFIG_DRM_AMDGPU_SI
206 extern int amdgpu_si_support;
207 #endif
208 #ifdef CONFIG_DRM_AMDGPU_CIK
209 extern int amdgpu_cik_support;
210 #endif
211 extern int amdgpu_num_kcq;
212
213 #define AMDGPU_VM_MAX_NUM_CTX 4096
214 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
215 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
216 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
217 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
218 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
219 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
220 #define AMDGPUFB_CONN_LIMIT 4
221 #define AMDGPU_BIOS_NUM_SCRATCH 16
222
223 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
224
225 /* hard reset data */
226 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
227
228 /* reset flags */
229 #define AMDGPU_RESET_GFX (1 << 0)
230 #define AMDGPU_RESET_COMPUTE (1 << 1)
231 #define AMDGPU_RESET_DMA (1 << 2)
232 #define AMDGPU_RESET_CP (1 << 3)
233 #define AMDGPU_RESET_GRBM (1 << 4)
234 #define AMDGPU_RESET_DMA1 (1 << 5)
235 #define AMDGPU_RESET_RLC (1 << 6)
236 #define AMDGPU_RESET_SEM (1 << 7)
237 #define AMDGPU_RESET_IH (1 << 8)
238 #define AMDGPU_RESET_VMC (1 << 9)
239 #define AMDGPU_RESET_MC (1 << 10)
240 #define AMDGPU_RESET_DISPLAY (1 << 11)
241 #define AMDGPU_RESET_UVD (1 << 12)
242 #define AMDGPU_RESET_VCE (1 << 13)
243 #define AMDGPU_RESET_VCE1 (1 << 14)
244
245 /* max cursor sizes (in pixels) */
246 #define CIK_CURSOR_WIDTH 128
247 #define CIK_CURSOR_HEIGHT 128
248
249 struct amdgpu_device;
250 struct amdgpu_ib;
251 struct amdgpu_cs_parser;
252 struct amdgpu_job;
253 struct amdgpu_irq_src;
254 struct amdgpu_fpriv;
255 struct amdgpu_bo_va_mapping;
256 struct amdgpu_atif;
257 struct kfd_vm_fault_info;
258 struct amdgpu_hive_info;
259
260 enum amdgpu_cp_irq {
261 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
262 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
263 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
266 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
267 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
270 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
271
272 AMDGPU_CP_IRQ_LAST
273 };
274
275 enum amdgpu_thermal_irq {
276 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
277 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
278
279 AMDGPU_THERMAL_IRQ_LAST
280 };
281
282 enum amdgpu_kiq_irq {
283 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
284 AMDGPU_CP_KIQ_IRQ_LAST
285 };
286 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
287 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
288 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
289 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
290
291 int amdgpu_device_ip_set_clockgating_state(void *dev,
292 enum amd_ip_block_type block_type,
293 enum amd_clockgating_state state);
294 int amdgpu_device_ip_set_powergating_state(void *dev,
295 enum amd_ip_block_type block_type,
296 enum amd_powergating_state state);
297 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
298 u32 *flags);
299 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
300 enum amd_ip_block_type block_type);
301 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
302 enum amd_ip_block_type block_type);
303
304 #define AMDGPU_MAX_IP_NUM 16
305
306 struct amdgpu_ip_block_status {
307 bool valid;
308 bool sw;
309 bool hw;
310 bool late_initialized;
311 bool hang;
312 };
313
314 struct amdgpu_ip_block_version {
315 const enum amd_ip_block_type type;
316 const u32 major;
317 const u32 minor;
318 const u32 rev;
319 const struct amd_ip_funcs *funcs;
320 };
321
322 #define HW_REV(_Major, _Minor, _Rev) \
323 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
324
325 struct amdgpu_ip_block {
326 struct amdgpu_ip_block_status status;
327 const struct amdgpu_ip_block_version *version;
328 };
329
330 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
331 enum amd_ip_block_type type,
332 u32 major, u32 minor);
333
334 struct amdgpu_ip_block *
335 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
336 enum amd_ip_block_type type);
337
338 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
339 const struct amdgpu_ip_block_version *ip_block_version);
340
341 /*
342 * BIOS.
343 */
344 bool amdgpu_get_bios(struct amdgpu_device *adev);
345 bool amdgpu_read_bios(struct amdgpu_device *adev);
346
347 /*
348 * Clocks
349 */
350
351 #define AMDGPU_MAX_PPLL 3
352
353 struct amdgpu_clock {
354 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
355 struct amdgpu_pll spll;
356 struct amdgpu_pll mpll;
357 /* 10 Khz units */
358 uint32_t default_mclk;
359 uint32_t default_sclk;
360 uint32_t default_dispclk;
361 uint32_t current_dispclk;
362 uint32_t dp_extclk;
363 uint32_t max_pixel_clock;
364 };
365
366 /* sub-allocation manager, it has to be protected by another lock.
367 * By conception this is an helper for other part of the driver
368 * like the indirect buffer or semaphore, which both have their
369 * locking.
370 *
371 * Principe is simple, we keep a list of sub allocation in offset
372 * order (first entry has offset == 0, last entry has the highest
373 * offset).
374 *
375 * When allocating new object we first check if there is room at
376 * the end total_size - (last_object_offset + last_object_size) >=
377 * alloc_size. If so we allocate new object there.
378 *
379 * When there is not enough room at the end, we start waiting for
380 * each sub object until we reach object_offset+object_size >=
381 * alloc_size, this object then become the sub object we return.
382 *
383 * Alignment can't be bigger than page size.
384 *
385 * Hole are not considered for allocation to keep things simple.
386 * Assumption is that there won't be hole (all object on same
387 * alignment).
388 */
389
390 #define AMDGPU_SA_NUM_FENCE_LISTS 32
391
392 struct amdgpu_sa_manager {
393 wait_queue_head_t wq;
394 struct amdgpu_bo *bo;
395 struct list_head *hole;
396 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
397 struct list_head olist;
398 unsigned size;
399 uint64_t gpu_addr;
400 void *cpu_ptr;
401 uint32_t domain;
402 uint32_t align;
403 };
404
405 /* sub-allocation buffer */
406 struct amdgpu_sa_bo {
407 struct list_head olist;
408 struct list_head flist;
409 struct amdgpu_sa_manager *manager;
410 unsigned soffset;
411 unsigned eoffset;
412 struct dma_fence *fence;
413 };
414
415 int amdgpu_fence_slab_init(void);
416 void amdgpu_fence_slab_fini(void);
417
418 /*
419 * IRQS.
420 */
421
422 struct amdgpu_flip_work {
423 struct delayed_work flip_work;
424 struct work_struct unpin_work;
425 struct amdgpu_device *adev;
426 int crtc_id;
427 u32 target_vblank;
428 uint64_t base;
429 struct drm_pending_vblank_event *event;
430 struct amdgpu_bo *old_abo;
431 struct dma_fence *excl;
432 unsigned shared_count;
433 struct dma_fence **shared;
434 struct dma_fence_cb cb;
435 bool async;
436 };
437
438
439 /*
440 * CP & rings.
441 */
442
443 struct amdgpu_ib {
444 struct amdgpu_sa_bo *sa_bo;
445 uint32_t length_dw;
446 uint64_t gpu_addr;
447 uint32_t *ptr;
448 uint32_t flags;
449 };
450
451 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
452
453 /*
454 * file private structure
455 */
456
457 struct amdgpu_fpriv {
458 struct amdgpu_vm vm;
459 struct amdgpu_bo_va *prt_va;
460 struct amdgpu_bo_va *csa_va;
461 struct mutex bo_list_lock;
462 struct idr bo_list_handles;
463 struct amdgpu_ctx_mgr ctx_mgr;
464 };
465
466 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
467
468 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
469 unsigned size,
470 enum amdgpu_ib_pool_type pool,
471 struct amdgpu_ib *ib);
472 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
473 struct dma_fence *f);
474 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
475 struct amdgpu_ib *ibs, struct amdgpu_job *job,
476 struct dma_fence **f);
477 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
478 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
479 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
480
481 /*
482 * CS.
483 */
484 struct amdgpu_cs_chunk {
485 uint32_t chunk_id;
486 uint32_t length_dw;
487 void *kdata;
488 };
489
490 struct amdgpu_cs_post_dep {
491 struct drm_syncobj *syncobj;
492 struct dma_fence_chain *chain;
493 u64 point;
494 };
495
496 struct amdgpu_cs_parser {
497 struct amdgpu_device *adev;
498 struct drm_file *filp;
499 struct amdgpu_ctx *ctx;
500
501 /* chunks */
502 unsigned nchunks;
503 struct amdgpu_cs_chunk *chunks;
504
505 /* scheduler job object */
506 struct amdgpu_job *job;
507 struct drm_sched_entity *entity;
508
509 /* buffer objects */
510 struct ww_acquire_ctx ticket;
511 struct amdgpu_bo_list *bo_list;
512 struct amdgpu_mn *mn;
513 struct amdgpu_bo_list_entry vm_pd;
514 struct list_head validated;
515 struct dma_fence *fence;
516 uint64_t bytes_moved_threshold;
517 uint64_t bytes_moved_vis_threshold;
518 uint64_t bytes_moved;
519 uint64_t bytes_moved_vis;
520
521 /* user fence */
522 struct amdgpu_bo_list_entry uf_entry;
523
524 unsigned num_post_deps;
525 struct amdgpu_cs_post_dep *post_deps;
526 };
527
amdgpu_get_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx)528 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
529 uint32_t ib_idx, int idx)
530 {
531 return p->job->ibs[ib_idx].ptr[idx];
532 }
533
amdgpu_set_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx,uint32_t value)534 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
535 uint32_t ib_idx, int idx,
536 uint32_t value)
537 {
538 p->job->ibs[ib_idx].ptr[idx] = value;
539 }
540
541 /*
542 * Writeback
543 */
544 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
545
546 struct amdgpu_wb {
547 struct amdgpu_bo *wb_obj;
548 volatile uint32_t *wb;
549 uint64_t gpu_addr;
550 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
551 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
552 };
553
554 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
555 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
556
557 /*
558 * Benchmarking
559 */
560 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
561
562
563 /*
564 * Testing
565 */
566 void amdgpu_test_moves(struct amdgpu_device *adev);
567
568 /*
569 * ASIC specific register table accessible by UMD
570 */
571 struct amdgpu_allowed_register_entry {
572 uint32_t reg_offset;
573 bool grbm_indexed;
574 };
575
576 enum amd_reset_method {
577 AMD_RESET_METHOD_LEGACY = 0,
578 AMD_RESET_METHOD_MODE0,
579 AMD_RESET_METHOD_MODE1,
580 AMD_RESET_METHOD_MODE2,
581 AMD_RESET_METHOD_BACO
582 };
583
584 /*
585 * ASIC specific functions.
586 */
587 struct amdgpu_asic_funcs {
588 bool (*read_disabled_bios)(struct amdgpu_device *adev);
589 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
590 u8 *bios, u32 length_bytes);
591 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
592 u32 sh_num, u32 reg_offset, u32 *value);
593 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
594 int (*reset)(struct amdgpu_device *adev);
595 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
596 /* get the reference clock */
597 u32 (*get_xclk)(struct amdgpu_device *adev);
598 /* MM block clocks */
599 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
600 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
601 /* static power management */
602 int (*get_pcie_lanes)(struct amdgpu_device *adev);
603 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
604 /* get config memsize register */
605 u32 (*get_config_memsize)(struct amdgpu_device *adev);
606 /* flush hdp write queue */
607 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
608 /* invalidate hdp read cache */
609 void (*invalidate_hdp)(struct amdgpu_device *adev,
610 struct amdgpu_ring *ring);
611 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
612 /* check if the asic needs a full reset of if soft reset will work */
613 bool (*need_full_reset)(struct amdgpu_device *adev);
614 /* initialize doorbell layout for specific asic*/
615 void (*init_doorbell_index)(struct amdgpu_device *adev);
616 /* PCIe bandwidth usage */
617 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
618 uint64_t *count1);
619 /* do we need to reset the asic at init time (e.g., kexec) */
620 bool (*need_reset_on_init)(struct amdgpu_device *adev);
621 /* PCIe replay counter */
622 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
623 /* device supports BACO */
624 bool (*supports_baco)(struct amdgpu_device *adev);
625 /* pre asic_init quirks */
626 void (*pre_asic_init)(struct amdgpu_device *adev);
627 };
628
629 /*
630 * IOCTL.
631 */
632 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
633 struct drm_file *filp);
634
635 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
636 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
637 struct drm_file *filp);
638 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
639 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
640 struct drm_file *filp);
641
642 /* VRAM scratch page for HDP bug, default vram page */
643 struct amdgpu_vram_scratch {
644 struct amdgpu_bo *robj;
645 volatile uint32_t *ptr;
646 u64 gpu_addr;
647 };
648
649 /*
650 * ACPI
651 */
652 struct amdgpu_atcs_functions {
653 bool get_ext_state;
654 bool pcie_perf_req;
655 bool pcie_dev_rdy;
656 bool pcie_bus_width;
657 };
658
659 struct amdgpu_atcs {
660 struct amdgpu_atcs_functions functions;
661 };
662
663 /*
664 * CGS
665 */
666 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
667 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
668
669 /*
670 * Core structure, functions and helpers.
671 */
672 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
673 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
674
675 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
676 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
677
678 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
679 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
680
681 struct amdgpu_mmio_remap {
682 u32 reg_offset;
683 resource_size_t bus_addr;
684 };
685
686 /* Define the HW IP blocks will be used in driver , add more if necessary */
687 enum amd_hw_ip_block_type {
688 GC_HWIP = 1,
689 HDP_HWIP,
690 SDMA0_HWIP,
691 SDMA1_HWIP,
692 SDMA2_HWIP,
693 SDMA3_HWIP,
694 SDMA4_HWIP,
695 SDMA5_HWIP,
696 SDMA6_HWIP,
697 SDMA7_HWIP,
698 MMHUB_HWIP,
699 ATHUB_HWIP,
700 NBIO_HWIP,
701 MP0_HWIP,
702 MP1_HWIP,
703 UVD_HWIP,
704 VCN_HWIP = UVD_HWIP,
705 JPEG_HWIP = VCN_HWIP,
706 VCE_HWIP,
707 DF_HWIP,
708 DCE_HWIP,
709 OSSSYS_HWIP,
710 SMUIO_HWIP,
711 PWR_HWIP,
712 NBIF_HWIP,
713 THM_HWIP,
714 CLK_HWIP,
715 UMC_HWIP,
716 RSMU_HWIP,
717 MAX_HWIP
718 };
719
720 #define HWIP_MAX_INSTANCE 10
721
722 struct amd_powerplay {
723 void *pp_handle;
724 const struct amd_pm_funcs *pp_funcs;
725 };
726
727 #define AMDGPU_RESET_MAGIC_NUM 64
728 #define AMDGPU_MAX_DF_PERFMONS 4
729 struct amdgpu_device {
730 struct device *dev;
731 struct pci_dev *pdev;
732 struct drm_device ddev;
733
734 #ifdef CONFIG_DRM_AMD_ACP
735 struct amdgpu_acp acp;
736 #endif
737 struct amdgpu_hive_info *hive;
738 /* ASIC */
739 enum amd_asic_type asic_type;
740 uint32_t family;
741 uint32_t rev_id;
742 uint32_t external_rev_id;
743 unsigned long flags;
744 unsigned long apu_flags;
745 int usec_timeout;
746 const struct amdgpu_asic_funcs *asic_funcs;
747 bool shutdown;
748 bool need_swiotlb;
749 bool accel_working;
750 struct notifier_block acpi_nb;
751 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
752 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
753 unsigned debugfs_count;
754 #if defined(CONFIG_DEBUG_FS)
755 struct dentry *debugfs_preempt;
756 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
757 #endif
758 struct amdgpu_atif *atif;
759 struct amdgpu_atcs atcs;
760 struct mutex srbm_mutex;
761 /* GRBM index mutex. Protects concurrent access to GRBM index */
762 struct mutex grbm_idx_mutex;
763 struct dev_pm_domain vga_pm_domain;
764 bool have_disp_power_ref;
765 bool have_atomics_support;
766
767 /* BIOS */
768 bool is_atom_fw;
769 uint8_t *bios;
770 uint32_t bios_size;
771 uint32_t bios_scratch_reg_offset;
772 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
773
774 /* Register/doorbell mmio */
775 resource_size_t rmmio_base;
776 resource_size_t rmmio_size;
777 void __iomem *rmmio;
778 /* protects concurrent MM_INDEX/DATA based register access */
779 spinlock_t mmio_idx_lock;
780 struct amdgpu_mmio_remap rmmio_remap;
781 /* protects concurrent SMC based register access */
782 spinlock_t smc_idx_lock;
783 amdgpu_rreg_t smc_rreg;
784 amdgpu_wreg_t smc_wreg;
785 /* protects concurrent PCIE register access */
786 spinlock_t pcie_idx_lock;
787 amdgpu_rreg_t pcie_rreg;
788 amdgpu_wreg_t pcie_wreg;
789 amdgpu_rreg_t pciep_rreg;
790 amdgpu_wreg_t pciep_wreg;
791 amdgpu_rreg64_t pcie_rreg64;
792 amdgpu_wreg64_t pcie_wreg64;
793 /* protects concurrent UVD register access */
794 spinlock_t uvd_ctx_idx_lock;
795 amdgpu_rreg_t uvd_ctx_rreg;
796 amdgpu_wreg_t uvd_ctx_wreg;
797 /* protects concurrent DIDT register access */
798 spinlock_t didt_idx_lock;
799 amdgpu_rreg_t didt_rreg;
800 amdgpu_wreg_t didt_wreg;
801 /* protects concurrent gc_cac register access */
802 spinlock_t gc_cac_idx_lock;
803 amdgpu_rreg_t gc_cac_rreg;
804 amdgpu_wreg_t gc_cac_wreg;
805 /* protects concurrent se_cac register access */
806 spinlock_t se_cac_idx_lock;
807 amdgpu_rreg_t se_cac_rreg;
808 amdgpu_wreg_t se_cac_wreg;
809 /* protects concurrent ENDPOINT (audio) register access */
810 spinlock_t audio_endpt_idx_lock;
811 amdgpu_block_rreg_t audio_endpt_rreg;
812 amdgpu_block_wreg_t audio_endpt_wreg;
813 void __iomem *rio_mem;
814 resource_size_t rio_mem_size;
815 struct amdgpu_doorbell doorbell;
816
817 /* clock/pll info */
818 struct amdgpu_clock clock;
819
820 /* MC */
821 struct amdgpu_gmc gmc;
822 struct amdgpu_gart gart;
823 dma_addr_t dummy_page_addr;
824 struct amdgpu_vm_manager vm_manager;
825 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
826 unsigned num_vmhubs;
827
828 /* memory management */
829 struct amdgpu_mman mman;
830 struct amdgpu_vram_scratch vram_scratch;
831 struct amdgpu_wb wb;
832 atomic64_t num_bytes_moved;
833 atomic64_t num_evictions;
834 atomic64_t num_vram_cpu_page_faults;
835 atomic_t gpu_reset_counter;
836 atomic_t vram_lost_counter;
837
838 /* data for buffer migration throttling */
839 struct {
840 spinlock_t lock;
841 s64 last_update_us;
842 s64 accum_us; /* accumulated microseconds */
843 s64 accum_us_vis; /* for visible VRAM */
844 u32 log2_max_MBps;
845 } mm_stats;
846
847 /* display */
848 bool enable_virtual_display;
849 struct amdgpu_mode_info mode_info;
850 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
851 struct work_struct hotplug_work;
852 struct amdgpu_irq_src crtc_irq;
853 struct amdgpu_irq_src vupdate_irq;
854 struct amdgpu_irq_src pageflip_irq;
855 struct amdgpu_irq_src hpd_irq;
856
857 /* rings */
858 u64 fence_context;
859 unsigned num_rings;
860 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
861 bool ib_pool_ready;
862 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
863 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
864
865 /* interrupts */
866 struct amdgpu_irq irq;
867
868 /* powerplay */
869 struct amd_powerplay powerplay;
870 bool pp_force_state_enabled;
871
872 /* smu */
873 struct smu_context smu;
874
875 /* dpm */
876 struct amdgpu_pm pm;
877 u32 cg_flags;
878 u32 pg_flags;
879
880 /* nbio */
881 struct amdgpu_nbio nbio;
882
883 /* mmhub */
884 struct amdgpu_mmhub mmhub;
885
886 /* gfxhub */
887 struct amdgpu_gfxhub gfxhub;
888
889 /* gfx */
890 struct amdgpu_gfx gfx;
891
892 /* sdma */
893 struct amdgpu_sdma sdma;
894
895 /* uvd */
896 struct amdgpu_uvd uvd;
897
898 /* vce */
899 struct amdgpu_vce vce;
900
901 /* vcn */
902 struct amdgpu_vcn vcn;
903
904 /* jpeg */
905 struct amdgpu_jpeg jpeg;
906
907 /* firmwares */
908 struct amdgpu_firmware firmware;
909
910 /* PSP */
911 struct psp_context psp;
912
913 /* GDS */
914 struct amdgpu_gds gds;
915
916 /* KFD */
917 struct amdgpu_kfd_dev kfd;
918
919 /* UMC */
920 struct amdgpu_umc umc;
921
922 /* display related functionality */
923 struct amdgpu_display_manager dm;
924
925 /* mes */
926 bool enable_mes;
927 struct amdgpu_mes mes;
928
929 /* df */
930 struct amdgpu_df df;
931
932 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
933 int num_ip_blocks;
934 struct mutex mn_lock;
935 DECLARE_HASHTABLE(mn_hash, 7);
936
937 /* tracking pinned memory */
938 atomic64_t vram_pin_size;
939 atomic64_t visible_pin_size;
940 atomic64_t gart_pin_size;
941
942 /* soc15 register offset based on ip, instance and segment */
943 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
944
945 /* delayed work_func for deferring clockgating during resume */
946 struct delayed_work delayed_init_work;
947
948 struct amdgpu_virt virt;
949
950 /* link all shadow bo */
951 struct list_head shadow_list;
952 struct mutex shadow_list_lock;
953
954 /* record hw reset is performed */
955 bool has_hw_reset;
956 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
957
958 /* s3/s4 mask */
959 bool in_suspend;
960 bool in_hibernate;
961
962 atomic_t in_gpu_reset;
963 enum pp_mp1_state mp1_state;
964 struct rw_semaphore reset_sem;
965 struct amdgpu_doorbell_index doorbell_index;
966
967 struct mutex notifier_lock;
968
969 int asic_reset_res;
970 struct work_struct xgmi_reset_work;
971
972 long gfx_timeout;
973 long sdma_timeout;
974 long video_timeout;
975 long compute_timeout;
976
977 uint64_t unique_id;
978 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
979
980 /* enable runtime pm on the device */
981 bool runpm;
982 bool in_runpm;
983
984 bool pm_sysfs_en;
985 bool ucode_sysfs_en;
986
987 /* Chip product information */
988 char product_number[16];
989 char product_name[32];
990 char serial[20];
991
992 struct amdgpu_autodump autodump;
993
994 atomic_t throttling_logging_enabled;
995 struct ratelimit_state throttling_logging_rs;
996 uint32_t ras_features;
997
998 bool in_pci_err_recovery;
999 struct pci_saved_state *pci_state;
1000 };
1001
drm_to_adev(struct drm_device * ddev)1002 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1003 {
1004 return container_of(ddev, struct amdgpu_device, ddev);
1005 }
1006
adev_to_drm(struct amdgpu_device * adev)1007 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1008 {
1009 return &adev->ddev;
1010 }
1011
amdgpu_ttm_adev(struct ttm_bo_device * bdev)1012 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1013 {
1014 return container_of(bdev, struct amdgpu_device, mman.bdev);
1015 }
1016
1017 int amdgpu_device_init(struct amdgpu_device *adev,
1018 uint32_t flags);
1019 void amdgpu_device_fini(struct amdgpu_device *adev);
1020 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1021
1022 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1023 uint32_t *buf, size_t size, bool write);
1024 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1025 uint32_t reg, uint32_t acc_flags);
1026 void amdgpu_device_wreg(struct amdgpu_device *adev,
1027 uint32_t reg, uint32_t v,
1028 uint32_t acc_flags);
1029 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1030 uint32_t reg, uint32_t v);
1031 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1032 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1033
1034 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1035 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1036
1037 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1038 u32 pcie_index, u32 pcie_data,
1039 u32 reg_addr);
1040 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1041 u32 pcie_index, u32 pcie_data,
1042 u32 reg_addr);
1043 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1044 u32 pcie_index, u32 pcie_data,
1045 u32 reg_addr, u32 reg_data);
1046 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1047 u32 pcie_index, u32 pcie_data,
1048 u32 reg_addr, u64 reg_data);
1049
1050 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1051 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1052
1053 int emu_soc_asic_init(struct amdgpu_device *adev);
1054
1055 /*
1056 * Registers read & write functions.
1057 */
1058 #define AMDGPU_REGS_NO_KIQ (1<<1)
1059
1060 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1061 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1062
1063 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1064 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1065
1066 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1067 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1068
1069 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1070 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1071 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1072 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1073 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1074 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1075 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1076 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1077 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1078 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1079 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1080 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1081 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1082 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1083 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1084 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1085 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1086 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1087 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1088 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1089 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1090 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1091 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1092 #define WREG32_P(reg, val, mask) \
1093 do { \
1094 uint32_t tmp_ = RREG32(reg); \
1095 tmp_ &= (mask); \
1096 tmp_ |= ((val) & ~(mask)); \
1097 WREG32(reg, tmp_); \
1098 } while (0)
1099 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1100 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1101 #define WREG32_PLL_P(reg, val, mask) \
1102 do { \
1103 uint32_t tmp_ = RREG32_PLL(reg); \
1104 tmp_ &= (mask); \
1105 tmp_ |= ((val) & ~(mask)); \
1106 WREG32_PLL(reg, tmp_); \
1107 } while (0)
1108
1109 #define WREG32_SMC_P(_Reg, _Val, _Mask) \
1110 do { \
1111 u32 tmp = RREG32_SMC(_Reg); \
1112 tmp &= (_Mask); \
1113 tmp |= ((_Val) & ~(_Mask)); \
1114 WREG32_SMC(_Reg, tmp); \
1115 } while (0)
1116
1117 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1118 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1119 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1120
1121 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1122 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1123
1124 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1125 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1126 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1127
1128 #define REG_GET_FIELD(value, reg, field) \
1129 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1130
1131 #define WREG32_FIELD(reg, field, val) \
1132 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1133
1134 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1135 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1136
1137 /*
1138 * BIOS helpers.
1139 */
1140 #define RBIOS8(i) (adev->bios[i])
1141 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1142 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1143
1144 /*
1145 * ASICs macro.
1146 */
1147 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1148 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1149 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1150 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1151 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1152 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1153 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1154 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1155 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1156 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1157 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1158 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1159 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1160 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1161 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1162 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1163 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1164 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1165 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1166 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1167 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1168 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1169
1170 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1171
1172 /* Common functions */
1173 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1174 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1175 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1176 struct amdgpu_job* job);
1177 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1178 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1179
1180 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1181 u64 num_vis_bytes);
1182 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1183 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1184 const u32 *registers,
1185 const u32 array_size);
1186
1187 bool amdgpu_device_supports_boco(struct drm_device *dev);
1188 bool amdgpu_device_supports_baco(struct drm_device *dev);
1189 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1190 struct amdgpu_device *peer_adev);
1191 int amdgpu_device_baco_enter(struct drm_device *dev);
1192 int amdgpu_device_baco_exit(struct drm_device *dev);
1193
1194 /* atpx handler */
1195 #if defined(CONFIG_VGA_SWITCHEROO)
1196 void amdgpu_register_atpx_handler(void);
1197 void amdgpu_unregister_atpx_handler(void);
1198 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1199 bool amdgpu_is_atpx_hybrid(void);
1200 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1201 bool amdgpu_has_atpx(void);
1202 #else
amdgpu_register_atpx_handler(void)1203 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1204 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1205 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1206 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1207 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1208 static inline bool amdgpu_has_atpx(void) { return false; }
1209 #endif
1210
1211 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1212 void *amdgpu_atpx_get_dhandle(void);
1213 #else
amdgpu_atpx_get_dhandle(void)1214 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1215 #endif
1216
1217 /*
1218 * KMS
1219 */
1220 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1221 extern const int amdgpu_max_kms_ioctl;
1222
1223 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1224 void amdgpu_driver_unload_kms(struct drm_device *dev);
1225 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1226 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1227 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1228 struct drm_file *file_priv);
1229 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1230 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1231 int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1232 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1233 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1234 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1235 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1236 unsigned long arg);
1237
1238 /*
1239 * functions used by amdgpu_encoder.c
1240 */
1241 struct amdgpu_afmt_acr {
1242 u32 clock;
1243
1244 int n_32khz;
1245 int cts_32khz;
1246
1247 int n_44_1khz;
1248 int cts_44_1khz;
1249
1250 int n_48khz;
1251 int cts_48khz;
1252
1253 };
1254
1255 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1256
1257 /* amdgpu_acpi.c */
1258 #if defined(CONFIG_ACPI)
1259 int amdgpu_acpi_init(struct amdgpu_device *adev);
1260 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1261 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1262 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1263 u8 perf_req, bool advertise);
1264 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1265
1266 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1267 struct amdgpu_dm_backlight_caps *caps);
1268 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1269 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_fini(struct amdgpu_device * adev)1270 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1271 #endif
1272
1273 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1274 uint64_t addr, struct amdgpu_bo **bo,
1275 struct amdgpu_bo_va_mapping **mapping);
1276
1277 #if defined(CONFIG_DRM_AMD_DC)
1278 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1279 #else
amdgpu_dm_display_resume(struct amdgpu_device * adev)1280 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1281 #endif
1282
1283
1284 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1285 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1286
1287 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1288 pci_channel_state_t state);
1289 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1290 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1291 void amdgpu_pci_resume(struct pci_dev *pdev);
1292
1293 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1294 bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1295
1296 #include "amdgpu_object.h"
1297
1298 /* used by df_v3_6.c and amdgpu_pmu.c */
1299 #define AMDGPU_PMU_ATTR(_name, _object) \
1300 static ssize_t \
1301 _name##_show(struct device *dev, \
1302 struct device_attribute *attr, \
1303 char *page) \
1304 { \
1305 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1306 return sprintf(page, _object "\n"); \
1307 } \
1308 \
1309 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1310
amdgpu_is_tmz(struct amdgpu_device * adev)1311 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1312 {
1313 return adev->gmc.tmz_enabled;
1314 }
1315
amdgpu_in_reset(struct amdgpu_device * adev)1316 static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1317 {
1318 return atomic_read(&adev->in_gpu_reset);
1319 }
1320 #endif
1321