1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RPC-IF core driver
4 *
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
6 * Copyright (C) 2019 Macronix International Co., Ltd.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18
19 #include <memory/renesas-rpc-if.h>
20
21 #define RPCIF_CMNCR 0x0000 /* R/W */
22 #define RPCIF_CMNCR_MD BIT(31)
23 #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */
24 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
25 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
26 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
27 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
28 #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \
29 RPCIF_CMNCR_MOIIO1(3) | \
30 RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3))
31 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */
32 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */
33 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
34 #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \
35 RPCIF_CMNCR_IO3FV(3))
36 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
37
38 #define RPCIF_SSLDR 0x0004 /* R/W */
39 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
40 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
41 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
42
43 #define RPCIF_DRCR 0x000C /* R/W */
44 #define RPCIF_DRCR_SSLN BIT(24)
45 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
46 #define RPCIF_DRCR_RCF BIT(9)
47 #define RPCIF_DRCR_RBE BIT(8)
48 #define RPCIF_DRCR_SSLE BIT(0)
49
50 #define RPCIF_DRCMR 0x0010 /* R/W */
51 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
52 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
53
54 #define RPCIF_DREAR 0x0014 /* R/W */
55 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
56 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
57
58 #define RPCIF_DROPR 0x0018 /* R/W */
59
60 #define RPCIF_DRENR 0x001C /* R/W */
61 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
62 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
63 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
64 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
65 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
66 #define RPCIF_DRENR_DME BIT(15)
67 #define RPCIF_DRENR_CDE BIT(14)
68 #define RPCIF_DRENR_OCDE BIT(12)
69 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
70 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
71
72 #define RPCIF_SMCR 0x0020 /* R/W */
73 #define RPCIF_SMCR_SSLKP BIT(8)
74 #define RPCIF_SMCR_SPIRE BIT(2)
75 #define RPCIF_SMCR_SPIWE BIT(1)
76 #define RPCIF_SMCR_SPIE BIT(0)
77
78 #define RPCIF_SMCMR 0x0024 /* R/W */
79 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
80 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
81
82 #define RPCIF_SMADR 0x0028 /* R/W */
83
84 #define RPCIF_SMOPR 0x002C /* R/W */
85 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
86 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
87 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
88 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
89
90 #define RPCIF_SMENR 0x0030 /* R/W */
91 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
92 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
93 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
94 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
95 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
96 #define RPCIF_SMENR_DME BIT(15)
97 #define RPCIF_SMENR_CDE BIT(14)
98 #define RPCIF_SMENR_OCDE BIT(12)
99 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
100 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
101 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
102
103 #define RPCIF_SMRDR0 0x0038 /* R */
104 #define RPCIF_SMRDR1 0x003C /* R */
105 #define RPCIF_SMWDR0 0x0040 /* W */
106 #define RPCIF_SMWDR1 0x0044 /* W */
107
108 #define RPCIF_CMNSR 0x0048 /* R */
109 #define RPCIF_CMNSR_SSLF BIT(1)
110 #define RPCIF_CMNSR_TEND BIT(0)
111
112 #define RPCIF_DRDMCR 0x0058 /* R/W */
113 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
114
115 #define RPCIF_DRDRENR 0x005C /* R/W */
116 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
117 #define RPCIF_DRDRENR_ADDRE BIT(8)
118 #define RPCIF_DRDRENR_OPDRE BIT(4)
119 #define RPCIF_DRDRENR_DRDRE BIT(0)
120
121 #define RPCIF_SMDMCR 0x0060 /* R/W */
122 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
123
124 #define RPCIF_SMDRENR 0x0064 /* R/W */
125 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
126 #define RPCIF_SMDRENR_ADDRE BIT(8)
127 #define RPCIF_SMDRENR_OPDRE BIT(4)
128 #define RPCIF_SMDRENR_SPIDRE BIT(0)
129
130 #define RPCIF_PHYCNT 0x007C /* R/W */
131 #define RPCIF_PHYCNT_CAL BIT(31)
132 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
133 #define RPCIF_PHYCNT_EXDS BIT(21)
134 #define RPCIF_PHYCNT_OCT BIT(20)
135 #define RPCIF_PHYCNT_DDRCAL BIT(19)
136 #define RPCIF_PHYCNT_HS BIT(18)
137 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
138 #define RPCIF_PHYCNT_WBUF2 BIT(4)
139 #define RPCIF_PHYCNT_WBUF BIT(2)
140 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
141
142 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */
143 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
144
145 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */
146 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
147
148 #define RPCIF_PHYINT 0x0088 /* R/W */
149 #define RPCIF_PHYINT_WPVAL BIT(1)
150
151 #define RPCIF_DIRMAP_SIZE 0x4000000
152
153 static const struct regmap_range rpcif_volatile_ranges[] = {
154 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
155 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
156 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
157 };
158
159 static const struct regmap_access_table rpcif_volatile_table = {
160 .yes_ranges = rpcif_volatile_ranges,
161 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
162 };
163
164
165 /*
166 * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
167 * proper width. Requires rpcif.xfer_size to be correctly set before!
168 */
rpcif_reg_read(void * context,unsigned int reg,unsigned int * val)169 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
170 {
171 struct rpcif *rpc = context;
172
173 switch (reg) {
174 case RPCIF_SMRDR0:
175 case RPCIF_SMWDR0:
176 switch (rpc->xfer_size) {
177 case 1:
178 *val = readb(rpc->base + reg);
179 return 0;
180
181 case 2:
182 *val = readw(rpc->base + reg);
183 return 0;
184
185 case 4:
186 case 8:
187 *val = readl(rpc->base + reg);
188 return 0;
189
190 default:
191 return -EILSEQ;
192 }
193
194 case RPCIF_SMRDR1:
195 case RPCIF_SMWDR1:
196 if (rpc->xfer_size != 8)
197 return -EILSEQ;
198 break;
199 }
200
201 *val = readl(rpc->base + reg);
202 return 0;
203
204 }
205
rpcif_reg_write(void * context,unsigned int reg,unsigned int val)206 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
207 {
208 struct rpcif *rpc = context;
209
210 switch (reg) {
211 case RPCIF_SMWDR0:
212 switch (rpc->xfer_size) {
213 case 1:
214 writeb(val, rpc->base + reg);
215 return 0;
216
217 case 2:
218 writew(val, rpc->base + reg);
219 return 0;
220
221 case 4:
222 case 8:
223 writel(val, rpc->base + reg);
224 return 0;
225
226 default:
227 return -EILSEQ;
228 }
229
230 case RPCIF_SMWDR1:
231 if (rpc->xfer_size != 8)
232 return -EILSEQ;
233 break;
234
235 case RPCIF_SMRDR0:
236 case RPCIF_SMRDR1:
237 return -EPERM;
238 }
239
240 writel(val, rpc->base + reg);
241 return 0;
242 }
243
244 static const struct regmap_config rpcif_regmap_config = {
245 .reg_bits = 32,
246 .val_bits = 32,
247 .reg_stride = 4,
248 .reg_read = rpcif_reg_read,
249 .reg_write = rpcif_reg_write,
250 .fast_io = true,
251 .max_register = RPCIF_PHYINT,
252 .volatile_table = &rpcif_volatile_table,
253 };
254
rpcif_sw_init(struct rpcif * rpc,struct device * dev)255 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
256 {
257 struct platform_device *pdev = to_platform_device(dev);
258 struct resource *res;
259
260 rpc->dev = dev;
261
262 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
263 rpc->base = devm_ioremap_resource(&pdev->dev, res);
264 if (IS_ERR(rpc->base))
265 return PTR_ERR(rpc->base);
266
267 rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
268 if (IS_ERR(rpc->regmap)) {
269 dev_err(&pdev->dev,
270 "failed to init regmap for rpcif, error %ld\n",
271 PTR_ERR(rpc->regmap));
272 return PTR_ERR(rpc->regmap);
273 }
274
275 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
276 rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
277 if (IS_ERR(rpc->dirmap))
278 return PTR_ERR(rpc->dirmap);
279 rpc->size = resource_size(res);
280
281 rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
282
283 return PTR_ERR_OR_ZERO(rpc->rstc);
284 }
285 EXPORT_SYMBOL(rpcif_sw_init);
286
rpcif_enable_rpm(struct rpcif * rpc)287 void rpcif_enable_rpm(struct rpcif *rpc)
288 {
289 pm_runtime_enable(rpc->dev);
290 }
291 EXPORT_SYMBOL(rpcif_enable_rpm);
292
rpcif_disable_rpm(struct rpcif * rpc)293 void rpcif_disable_rpm(struct rpcif *rpc)
294 {
295 pm_runtime_disable(rpc->dev);
296 }
297 EXPORT_SYMBOL(rpcif_disable_rpm);
298
rpcif_hw_init(struct rpcif * rpc,bool hyperflash)299 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
300 {
301 u32 dummy;
302
303 pm_runtime_get_sync(rpc->dev);
304
305 /*
306 * NOTE: The 0x260 are undocumented bits, but they must be set.
307 * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits,
308 * 0x0 : the delay is biggest,
309 * 0x1 : the delay is 2nd biggest,
310 * On H3 ES1.x, the value should be 0, while on others,
311 * the value should be 7.
312 */
313 regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) |
314 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260);
315
316 /*
317 * NOTE: The 0x1511144 are undocumented bits, but they must be set
318 * for RPCIF_PHYOFFSET1.
319 * The 0x31 are undocumented bits, but they must be set
320 * for RPCIF_PHYOFFSET2.
321 */
322 regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 |
323 RPCIF_PHYOFFSET1_DDRTMG(3));
324 regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 |
325 RPCIF_PHYOFFSET2_OCTTMG(4));
326
327 if (hyperflash)
328 regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
329 RPCIF_PHYINT_WPVAL, 0);
330
331 regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE |
332 RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ |
333 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
334 /* Set RCF after BSZ update */
335 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
336 /* Dummy read according to spec */
337 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
338 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
339 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
340
341 pm_runtime_put(rpc->dev);
342
343 rpc->bus_size = hyperflash ? 2 : 1;
344 }
345 EXPORT_SYMBOL(rpcif_hw_init);
346
wait_msg_xfer_end(struct rpcif * rpc)347 static int wait_msg_xfer_end(struct rpcif *rpc)
348 {
349 u32 sts;
350
351 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
352 sts & RPCIF_CMNSR_TEND, 0,
353 USEC_PER_SEC);
354 }
355
rpcif_bits_set(struct rpcif * rpc,u32 nbytes)356 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
357 {
358 if (rpc->bus_size == 2)
359 nbytes /= 2;
360 nbytes = clamp(nbytes, 1U, 4U);
361 return GENMASK(3, 4 - nbytes);
362 }
363
rpcif_bit_size(u8 buswidth)364 static u8 rpcif_bit_size(u8 buswidth)
365 {
366 return buswidth > 4 ? 2 : ilog2(buswidth);
367 }
368
rpcif_prepare(struct rpcif * rpc,const struct rpcif_op * op,u64 * offs,size_t * len)369 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
370 size_t *len)
371 {
372 rpc->smcr = 0;
373 rpc->smadr = 0;
374 rpc->enable = 0;
375 rpc->command = 0;
376 rpc->option = 0;
377 rpc->dummy = 0;
378 rpc->ddr = 0;
379 rpc->xferlen = 0;
380
381 if (op->cmd.buswidth) {
382 rpc->enable = RPCIF_SMENR_CDE |
383 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
384 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
385 if (op->cmd.ddr)
386 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
387 }
388 if (op->ocmd.buswidth) {
389 rpc->enable |= RPCIF_SMENR_OCDE |
390 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
391 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
392 }
393
394 if (op->addr.buswidth) {
395 rpc->enable |=
396 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
397 if (op->addr.nbytes == 4)
398 rpc->enable |= RPCIF_SMENR_ADE(0xF);
399 else
400 rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
401 2, 3 - op->addr.nbytes));
402 if (op->addr.ddr)
403 rpc->ddr |= RPCIF_SMDRENR_ADDRE;
404
405 if (offs && len)
406 rpc->smadr = *offs;
407 else
408 rpc->smadr = op->addr.val;
409 }
410
411 if (op->dummy.buswidth) {
412 rpc->enable |= RPCIF_SMENR_DME;
413 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
414 op->dummy.buswidth);
415 }
416
417 if (op->option.buswidth) {
418 rpc->enable |= RPCIF_SMENR_OPDE(
419 rpcif_bits_set(rpc, op->option.nbytes)) |
420 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
421 if (op->option.ddr)
422 rpc->ddr |= RPCIF_SMDRENR_OPDRE;
423 rpc->option = op->option.val;
424 }
425
426 rpc->dir = op->data.dir;
427 if (op->data.buswidth) {
428 u32 nbytes;
429
430 rpc->buffer = op->data.buf.in;
431 switch (op->data.dir) {
432 case RPCIF_DATA_IN:
433 rpc->smcr = RPCIF_SMCR_SPIRE;
434 break;
435 case RPCIF_DATA_OUT:
436 rpc->smcr = RPCIF_SMCR_SPIWE;
437 break;
438 default:
439 break;
440 }
441 if (op->data.ddr)
442 rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
443
444 if (offs && len)
445 nbytes = *len;
446 else
447 nbytes = op->data.nbytes;
448 rpc->xferlen = nbytes;
449
450 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
451 }
452 }
453 EXPORT_SYMBOL(rpcif_prepare);
454
rpcif_manual_xfer(struct rpcif * rpc)455 int rpcif_manual_xfer(struct rpcif *rpc)
456 {
457 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
458 int ret = 0;
459
460 pm_runtime_get_sync(rpc->dev);
461
462 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
463 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
464 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
465 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
466 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
467 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
468 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
469 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
470 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
471 smenr = rpc->enable;
472
473 switch (rpc->dir) {
474 case RPCIF_DATA_OUT:
475 while (pos < rpc->xferlen) {
476 u32 bytes_left = rpc->xferlen - pos;
477 u32 nbytes, data[2];
478
479 smcr = rpc->smcr | RPCIF_SMCR_SPIE;
480
481 /* nbytes may only be 1, 2, 4, or 8 */
482 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
483 if (bytes_left > nbytes)
484 smcr |= RPCIF_SMCR_SSLKP;
485
486 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
487 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
488 rpc->xfer_size = nbytes;
489
490 memcpy(data, rpc->buffer + pos, nbytes);
491 if (nbytes == 8) {
492 regmap_write(rpc->regmap, RPCIF_SMWDR1,
493 data[0]);
494 regmap_write(rpc->regmap, RPCIF_SMWDR0,
495 data[1]);
496 } else {
497 regmap_write(rpc->regmap, RPCIF_SMWDR0,
498 data[0]);
499 }
500
501 regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
502 ret = wait_msg_xfer_end(rpc);
503 if (ret)
504 goto err_out;
505
506 pos += nbytes;
507 smenr = rpc->enable &
508 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
509 }
510 break;
511 case RPCIF_DATA_IN:
512 /*
513 * RPC-IF spoils the data for the commands without an address
514 * phase (like RDID) in the manual mode, so we'll have to work
515 * around this issue by using the external address space read
516 * mode instead.
517 */
518 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
519 u32 dummy;
520
521 regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
522 RPCIF_CMNCR_MD, 0);
523 regmap_write(rpc->regmap, RPCIF_DRCR,
524 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
525 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
526 regmap_write(rpc->regmap, RPCIF_DREAR,
527 RPCIF_DREAR_EAC(1));
528 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
529 regmap_write(rpc->regmap, RPCIF_DRENR,
530 smenr & ~RPCIF_SMENR_SPIDE(0xF));
531 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
532 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
533 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
534 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
535 /* Dummy read according to spec */
536 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
537 break;
538 }
539 while (pos < rpc->xferlen) {
540 u32 bytes_left = rpc->xferlen - pos;
541 u32 nbytes, data[2];
542
543 /* nbytes may only be 1, 2, 4, or 8 */
544 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
545
546 regmap_write(rpc->regmap, RPCIF_SMADR,
547 rpc->smadr + pos);
548 smenr &= ~RPCIF_SMENR_SPIDE(0xF);
549 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
550 regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
551 regmap_write(rpc->regmap, RPCIF_SMCR,
552 rpc->smcr | RPCIF_SMCR_SPIE);
553 rpc->xfer_size = nbytes;
554 ret = wait_msg_xfer_end(rpc);
555 if (ret)
556 goto err_out;
557
558 if (nbytes == 8) {
559 regmap_read(rpc->regmap, RPCIF_SMRDR1,
560 &data[0]);
561 regmap_read(rpc->regmap, RPCIF_SMRDR0,
562 &data[1]);
563 } else {
564 regmap_read(rpc->regmap, RPCIF_SMRDR0,
565 &data[0]);
566 }
567 memcpy(rpc->buffer + pos, data, nbytes);
568
569 pos += nbytes;
570 }
571 break;
572 default:
573 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
574 regmap_write(rpc->regmap, RPCIF_SMCR,
575 rpc->smcr | RPCIF_SMCR_SPIE);
576 ret = wait_msg_xfer_end(rpc);
577 if (ret)
578 goto err_out;
579 }
580
581 exit:
582 pm_runtime_put(rpc->dev);
583 return ret;
584
585 err_out:
586 if (reset_control_reset(rpc->rstc))
587 dev_err(rpc->dev, "Failed to reset HW\n");
588 rpcif_hw_init(rpc, rpc->bus_size == 2);
589 goto exit;
590 }
591 EXPORT_SYMBOL(rpcif_manual_xfer);
592
rpcif_dirmap_read(struct rpcif * rpc,u64 offs,size_t len,void * buf)593 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
594 {
595 loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1);
596 size_t size = RPCIF_DIRMAP_SIZE - from;
597
598 if (len > size)
599 len = size;
600
601 pm_runtime_get_sync(rpc->dev);
602
603 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
604 regmap_write(rpc->regmap, RPCIF_DRCR, 0);
605 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
606 regmap_write(rpc->regmap, RPCIF_DREAR,
607 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
608 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
609 regmap_write(rpc->regmap, RPCIF_DRENR,
610 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
611 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
612 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
613
614 memcpy_fromio(buf, rpc->dirmap + from, len);
615
616 pm_runtime_put(rpc->dev);
617
618 return len;
619 }
620 EXPORT_SYMBOL(rpcif_dirmap_read);
621
rpcif_probe(struct platform_device * pdev)622 static int rpcif_probe(struct platform_device *pdev)
623 {
624 struct platform_device *vdev;
625 struct device_node *flash;
626 const char *name;
627 int ret;
628
629 flash = of_get_next_child(pdev->dev.of_node, NULL);
630 if (!flash) {
631 dev_warn(&pdev->dev, "no flash node found\n");
632 return -ENODEV;
633 }
634
635 if (of_device_is_compatible(flash, "jedec,spi-nor")) {
636 name = "rpc-if-spi";
637 } else if (of_device_is_compatible(flash, "cfi-flash")) {
638 name = "rpc-if-hyperflash";
639 } else {
640 of_node_put(flash);
641 dev_warn(&pdev->dev, "unknown flash type\n");
642 return -ENODEV;
643 }
644 of_node_put(flash);
645
646 vdev = platform_device_alloc(name, pdev->id);
647 if (!vdev)
648 return -ENOMEM;
649 vdev->dev.parent = &pdev->dev;
650 platform_set_drvdata(pdev, vdev);
651
652 ret = platform_device_add(vdev);
653 if (ret) {
654 platform_device_put(vdev);
655 return ret;
656 }
657
658 return 0;
659 }
660
rpcif_remove(struct platform_device * pdev)661 static int rpcif_remove(struct platform_device *pdev)
662 {
663 struct platform_device *vdev = platform_get_drvdata(pdev);
664
665 platform_device_unregister(vdev);
666
667 return 0;
668 }
669
670 static const struct of_device_id rpcif_of_match[] = {
671 { .compatible = "renesas,rcar-gen3-rpc-if", },
672 {},
673 };
674 MODULE_DEVICE_TABLE(of, rpcif_of_match);
675
676 static struct platform_driver rpcif_driver = {
677 .probe = rpcif_probe,
678 .remove = rpcif_remove,
679 .driver = {
680 .name = "rpc-if",
681 .of_match_table = rpcif_of_match,
682 },
683 };
684 module_platform_driver(rpcif_driver);
685
686 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
687 MODULE_LICENSE("GPL v2");
688