1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 *
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 *
7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/ktime.h>
16 #include <linux/highmem.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/sizes.h>
23 #include <linux/swiotlb.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27
28 #include <linux/leds.h>
29
30 #include <linux/mmc/mmc.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include <trace/hooks/mmc_core.h>
37
38 #include "sdhci.h"
39
40 #define DRIVER_NAME "sdhci"
41
42 #define DBG(f, x...) \
43 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
45 #define SDHCI_DUMP(f, x...) \
46 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
47
48 #define MAX_TUNING_LOOP 40
49
50 static unsigned int debug_quirks = 0;
51 static unsigned int debug_quirks2;
52
53 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
54
55 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
56
sdhci_dumpregs(struct sdhci_host * host)57 void sdhci_dumpregs(struct sdhci_host *host)
58 {
59 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
60
61 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
62 sdhci_readl(host, SDHCI_DMA_ADDRESS),
63 sdhci_readw(host, SDHCI_HOST_VERSION));
64 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
65 sdhci_readw(host, SDHCI_BLOCK_SIZE),
66 sdhci_readw(host, SDHCI_BLOCK_COUNT));
67 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
68 sdhci_readl(host, SDHCI_ARGUMENT),
69 sdhci_readw(host, SDHCI_TRANSFER_MODE));
70 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
71 sdhci_readl(host, SDHCI_PRESENT_STATE),
72 sdhci_readb(host, SDHCI_HOST_CONTROL));
73 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
74 sdhci_readb(host, SDHCI_POWER_CONTROL),
75 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
76 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
77 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
78 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
79 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
80 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
81 sdhci_readl(host, SDHCI_INT_STATUS));
82 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
83 sdhci_readl(host, SDHCI_INT_ENABLE),
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
85 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
86 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
87 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
88 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
89 sdhci_readl(host, SDHCI_CAPABILITIES),
90 sdhci_readl(host, SDHCI_CAPABILITIES_1));
91 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
92 sdhci_readw(host, SDHCI_COMMAND),
93 sdhci_readl(host, SDHCI_MAX_CURRENT));
94 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
95 sdhci_readl(host, SDHCI_RESPONSE),
96 sdhci_readl(host, SDHCI_RESPONSE + 4));
97 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
98 sdhci_readl(host, SDHCI_RESPONSE + 8),
99 sdhci_readl(host, SDHCI_RESPONSE + 12));
100 SDHCI_DUMP("Host ctl2: 0x%08x\n",
101 sdhci_readw(host, SDHCI_HOST_CONTROL2));
102
103 if (host->flags & SDHCI_USE_ADMA) {
104 if (host->flags & SDHCI_USE_64_BIT_DMA) {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
109 } else {
110 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
111 sdhci_readl(host, SDHCI_ADMA_ERROR),
112 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 }
114 }
115
116 if (host->ops->dump_vendor_regs)
117 host->ops->dump_vendor_regs(host);
118
119 SDHCI_DUMP("============================================\n");
120 }
121 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
122
123 /*****************************************************************************\
124 * *
125 * Low level functions *
126 * *
127 \*****************************************************************************/
128
sdhci_do_enable_v4_mode(struct sdhci_host * host)129 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
130 {
131 u16 ctrl2;
132
133 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
134 if (ctrl2 & SDHCI_CTRL_V4_MODE)
135 return;
136
137 ctrl2 |= SDHCI_CTRL_V4_MODE;
138 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
139 }
140
141 /*
142 * This can be called before sdhci_add_host() by Vendor's host controller
143 * driver to enable v4 mode if supported.
144 */
sdhci_enable_v4_mode(struct sdhci_host * host)145 void sdhci_enable_v4_mode(struct sdhci_host *host)
146 {
147 host->v4_mode = true;
148 sdhci_do_enable_v4_mode(host);
149 }
150 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
151
sdhci_data_line_cmd(struct mmc_command * cmd)152 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
153 {
154 return cmd->data || cmd->flags & MMC_RSP_BUSY;
155 }
156
sdhci_set_card_detection(struct sdhci_host * host,bool enable)157 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
158 {
159 u32 present;
160
161 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
162 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
163 return;
164
165 if (enable) {
166 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
167 SDHCI_CARD_PRESENT;
168
169 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
170 SDHCI_INT_CARD_INSERT;
171 } else {
172 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
173 }
174
175 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
176 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
177 }
178
sdhci_enable_card_detection(struct sdhci_host * host)179 static void sdhci_enable_card_detection(struct sdhci_host *host)
180 {
181 sdhci_set_card_detection(host, true);
182 }
183
sdhci_disable_card_detection(struct sdhci_host * host)184 static void sdhci_disable_card_detection(struct sdhci_host *host)
185 {
186 sdhci_set_card_detection(host, false);
187 }
188
sdhci_runtime_pm_bus_on(struct sdhci_host * host)189 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
190 {
191 if (host->bus_on)
192 return;
193 host->bus_on = true;
194 pm_runtime_get_noresume(host->mmc->parent);
195 }
196
sdhci_runtime_pm_bus_off(struct sdhci_host * host)197 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
198 {
199 if (!host->bus_on)
200 return;
201 host->bus_on = false;
202 pm_runtime_put_noidle(host->mmc->parent);
203 }
204
sdhci_reset(struct sdhci_host * host,u8 mask)205 void sdhci_reset(struct sdhci_host *host, u8 mask)
206 {
207 ktime_t timeout;
208
209 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
210
211 if (mask & SDHCI_RESET_ALL) {
212 host->clock = 0;
213 /* Reset-all turns off SD Bus Power */
214 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
215 sdhci_runtime_pm_bus_off(host);
216 }
217
218 /* Wait max 100 ms */
219 timeout = ktime_add_ms(ktime_get(), 100);
220
221 /* hw clears the bit when it's done */
222 while (1) {
223 bool timedout = ktime_after(ktime_get(), timeout);
224
225 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
226 break;
227 if (timedout) {
228 pr_err("%s: Reset 0x%x never completed.\n",
229 mmc_hostname(host->mmc), (int)mask);
230 sdhci_dumpregs(host);
231 return;
232 }
233 udelay(10);
234 }
235 }
236 EXPORT_SYMBOL_GPL(sdhci_reset);
237
sdhci_do_reset(struct sdhci_host * host,u8 mask)238 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
239 {
240 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
241 struct mmc_host *mmc = host->mmc;
242
243 if (!mmc->ops->get_cd(mmc))
244 return;
245 }
246
247 host->ops->reset(host, mask);
248
249 if (mask & SDHCI_RESET_ALL) {
250 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
251 if (host->ops->enable_dma)
252 host->ops->enable_dma(host);
253 }
254
255 /* Resetting the controller clears many */
256 host->preset_enabled = false;
257 }
258 }
259
sdhci_set_default_irqs(struct sdhci_host * host)260 static void sdhci_set_default_irqs(struct sdhci_host *host)
261 {
262 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
263 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
264 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
265 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
266 SDHCI_INT_RESPONSE;
267
268 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
269 host->tuning_mode == SDHCI_TUNING_MODE_3)
270 host->ier |= SDHCI_INT_RETUNE;
271
272 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
273 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
274 }
275
sdhci_config_dma(struct sdhci_host * host)276 static void sdhci_config_dma(struct sdhci_host *host)
277 {
278 u8 ctrl;
279 u16 ctrl2;
280
281 if (host->version < SDHCI_SPEC_200)
282 return;
283
284 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
285
286 /*
287 * Always adjust the DMA selection as some controllers
288 * (e.g. JMicron) can't do PIO properly when the selection
289 * is ADMA.
290 */
291 ctrl &= ~SDHCI_CTRL_DMA_MASK;
292 if (!(host->flags & SDHCI_REQ_USE_DMA))
293 goto out;
294
295 /* Note if DMA Select is zero then SDMA is selected */
296 if (host->flags & SDHCI_USE_ADMA)
297 ctrl |= SDHCI_CTRL_ADMA32;
298
299 if (host->flags & SDHCI_USE_64_BIT_DMA) {
300 /*
301 * If v4 mode, all supported DMA can be 64-bit addressing if
302 * controller supports 64-bit system address, otherwise only
303 * ADMA can support 64-bit addressing.
304 */
305 if (host->v4_mode) {
306 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
307 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
308 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
309 } else if (host->flags & SDHCI_USE_ADMA) {
310 /*
311 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
312 * set SDHCI_CTRL_ADMA64.
313 */
314 ctrl |= SDHCI_CTRL_ADMA64;
315 }
316 }
317
318 out:
319 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
320 }
321
sdhci_init(struct sdhci_host * host,int soft)322 static void sdhci_init(struct sdhci_host *host, int soft)
323 {
324 struct mmc_host *mmc = host->mmc;
325 unsigned long flags;
326
327 if (soft)
328 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
329 else
330 sdhci_do_reset(host, SDHCI_RESET_ALL);
331
332 if (host->v4_mode)
333 sdhci_do_enable_v4_mode(host);
334
335 spin_lock_irqsave(&host->lock, flags);
336 sdhci_set_default_irqs(host);
337 spin_unlock_irqrestore(&host->lock, flags);
338
339 host->cqe_on = false;
340
341 if (soft) {
342 /* force clock reconfiguration */
343 host->clock = 0;
344 mmc->ops->set_ios(mmc, &mmc->ios);
345 }
346 }
347
sdhci_reinit(struct sdhci_host * host)348 static void sdhci_reinit(struct sdhci_host *host)
349 {
350 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
351
352 sdhci_init(host, 0);
353 sdhci_enable_card_detection(host);
354
355 /*
356 * A change to the card detect bits indicates a change in present state,
357 * refer sdhci_set_card_detection(). A card detect interrupt might have
358 * been missed while the host controller was being reset, so trigger a
359 * rescan to check.
360 */
361 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
362 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
363 }
364
__sdhci_led_activate(struct sdhci_host * host)365 static void __sdhci_led_activate(struct sdhci_host *host)
366 {
367 u8 ctrl;
368
369 if (host->quirks & SDHCI_QUIRK_NO_LED)
370 return;
371
372 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
373 ctrl |= SDHCI_CTRL_LED;
374 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
375 }
376
__sdhci_led_deactivate(struct sdhci_host * host)377 static void __sdhci_led_deactivate(struct sdhci_host *host)
378 {
379 u8 ctrl;
380
381 if (host->quirks & SDHCI_QUIRK_NO_LED)
382 return;
383
384 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
385 ctrl &= ~SDHCI_CTRL_LED;
386 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
387 }
388
389 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
sdhci_led_control(struct led_classdev * led,enum led_brightness brightness)390 static void sdhci_led_control(struct led_classdev *led,
391 enum led_brightness brightness)
392 {
393 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
394 unsigned long flags;
395
396 spin_lock_irqsave(&host->lock, flags);
397
398 if (host->runtime_suspended)
399 goto out;
400
401 if (brightness == LED_OFF)
402 __sdhci_led_deactivate(host);
403 else
404 __sdhci_led_activate(host);
405 out:
406 spin_unlock_irqrestore(&host->lock, flags);
407 }
408
sdhci_led_register(struct sdhci_host * host)409 static int sdhci_led_register(struct sdhci_host *host)
410 {
411 struct mmc_host *mmc = host->mmc;
412
413 if (host->quirks & SDHCI_QUIRK_NO_LED)
414 return 0;
415
416 snprintf(host->led_name, sizeof(host->led_name),
417 "%s::", mmc_hostname(mmc));
418
419 host->led.name = host->led_name;
420 host->led.brightness = LED_OFF;
421 host->led.default_trigger = mmc_hostname(mmc);
422 host->led.brightness_set = sdhci_led_control;
423
424 return led_classdev_register(mmc_dev(mmc), &host->led);
425 }
426
sdhci_led_unregister(struct sdhci_host * host)427 static void sdhci_led_unregister(struct sdhci_host *host)
428 {
429 if (host->quirks & SDHCI_QUIRK_NO_LED)
430 return;
431
432 led_classdev_unregister(&host->led);
433 }
434
sdhci_led_activate(struct sdhci_host * host)435 static inline void sdhci_led_activate(struct sdhci_host *host)
436 {
437 }
438
sdhci_led_deactivate(struct sdhci_host * host)439 static inline void sdhci_led_deactivate(struct sdhci_host *host)
440 {
441 }
442
443 #else
444
sdhci_led_register(struct sdhci_host * host)445 static inline int sdhci_led_register(struct sdhci_host *host)
446 {
447 return 0;
448 }
449
sdhci_led_unregister(struct sdhci_host * host)450 static inline void sdhci_led_unregister(struct sdhci_host *host)
451 {
452 }
453
sdhci_led_activate(struct sdhci_host * host)454 static inline void sdhci_led_activate(struct sdhci_host *host)
455 {
456 __sdhci_led_activate(host);
457 }
458
sdhci_led_deactivate(struct sdhci_host * host)459 static inline void sdhci_led_deactivate(struct sdhci_host *host)
460 {
461 __sdhci_led_deactivate(host);
462 }
463
464 #endif
465
sdhci_mod_timer(struct sdhci_host * host,struct mmc_request * mrq,unsigned long timeout)466 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
467 unsigned long timeout)
468 {
469 if (sdhci_data_line_cmd(mrq->cmd))
470 mod_timer(&host->data_timer, timeout);
471 else
472 mod_timer(&host->timer, timeout);
473 }
474
sdhci_del_timer(struct sdhci_host * host,struct mmc_request * mrq)475 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
476 {
477 if (sdhci_data_line_cmd(mrq->cmd))
478 del_timer(&host->data_timer);
479 else
480 del_timer(&host->timer);
481 }
482
sdhci_has_requests(struct sdhci_host * host)483 static inline bool sdhci_has_requests(struct sdhci_host *host)
484 {
485 return host->cmd || host->data_cmd;
486 }
487
488 /*****************************************************************************\
489 * *
490 * Core functions *
491 * *
492 \*****************************************************************************/
493
sdhci_read_block_pio(struct sdhci_host * host)494 static void sdhci_read_block_pio(struct sdhci_host *host)
495 {
496 unsigned long flags;
497 size_t blksize, len, chunk;
498 u32 scratch;
499 u8 *buf;
500
501 DBG("PIO reading\n");
502
503 blksize = host->data->blksz;
504 chunk = 0;
505
506 local_irq_save(flags);
507
508 while (blksize) {
509 BUG_ON(!sg_miter_next(&host->sg_miter));
510
511 len = min(host->sg_miter.length, blksize);
512
513 blksize -= len;
514 host->sg_miter.consumed = len;
515
516 buf = host->sg_miter.addr;
517
518 while (len) {
519 if (chunk == 0) {
520 scratch = sdhci_readl(host, SDHCI_BUFFER);
521 chunk = 4;
522 }
523
524 *buf = scratch & 0xFF;
525
526 buf++;
527 scratch >>= 8;
528 chunk--;
529 len--;
530 }
531 }
532
533 sg_miter_stop(&host->sg_miter);
534
535 local_irq_restore(flags);
536 }
537
sdhci_write_block_pio(struct sdhci_host * host)538 static void sdhci_write_block_pio(struct sdhci_host *host)
539 {
540 unsigned long flags;
541 size_t blksize, len, chunk;
542 u32 scratch;
543 u8 *buf;
544
545 DBG("PIO writing\n");
546
547 blksize = host->data->blksz;
548 chunk = 0;
549 scratch = 0;
550
551 local_irq_save(flags);
552
553 while (blksize) {
554 BUG_ON(!sg_miter_next(&host->sg_miter));
555
556 len = min(host->sg_miter.length, blksize);
557
558 blksize -= len;
559 host->sg_miter.consumed = len;
560
561 buf = host->sg_miter.addr;
562
563 while (len) {
564 scratch |= (u32)*buf << (chunk * 8);
565
566 buf++;
567 chunk++;
568 len--;
569
570 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
571 sdhci_writel(host, scratch, SDHCI_BUFFER);
572 chunk = 0;
573 scratch = 0;
574 }
575 }
576 }
577
578 sg_miter_stop(&host->sg_miter);
579
580 local_irq_restore(flags);
581 }
582
sdhci_transfer_pio(struct sdhci_host * host)583 static void sdhci_transfer_pio(struct sdhci_host *host)
584 {
585 u32 mask;
586
587 if (host->blocks == 0)
588 return;
589
590 if (host->data->flags & MMC_DATA_READ)
591 mask = SDHCI_DATA_AVAILABLE;
592 else
593 mask = SDHCI_SPACE_AVAILABLE;
594
595 /*
596 * Some controllers (JMicron JMB38x) mess up the buffer bits
597 * for transfers < 4 bytes. As long as it is just one block,
598 * we can ignore the bits.
599 */
600 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
601 (host->data->blocks == 1))
602 mask = ~0;
603
604 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
605 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
606 udelay(100);
607
608 if (host->data->flags & MMC_DATA_READ)
609 sdhci_read_block_pio(host);
610 else
611 sdhci_write_block_pio(host);
612
613 host->blocks--;
614 if (host->blocks == 0)
615 break;
616 }
617
618 DBG("PIO transfer complete.\n");
619 }
620
sdhci_pre_dma_transfer(struct sdhci_host * host,struct mmc_data * data,int cookie)621 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
622 struct mmc_data *data, int cookie)
623 {
624 int sg_count;
625
626 /*
627 * If the data buffers are already mapped, return the previous
628 * dma_map_sg() result.
629 */
630 if (data->host_cookie == COOKIE_PRE_MAPPED)
631 return data->sg_count;
632
633 /* Bounce write requests to the bounce buffer */
634 if (host->bounce_buffer) {
635 unsigned int length = data->blksz * data->blocks;
636
637 if (length > host->bounce_buffer_size) {
638 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
639 mmc_hostname(host->mmc), length,
640 host->bounce_buffer_size);
641 return -EIO;
642 }
643 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
644 /* Copy the data to the bounce buffer */
645 if (host->ops->copy_to_bounce_buffer) {
646 host->ops->copy_to_bounce_buffer(host,
647 data, length);
648 } else {
649 sg_copy_to_buffer(data->sg, data->sg_len,
650 host->bounce_buffer, length);
651 }
652 }
653 /* Switch ownership to the DMA */
654 dma_sync_single_for_device(host->mmc->parent,
655 host->bounce_addr,
656 host->bounce_buffer_size,
657 mmc_get_dma_dir(data));
658 /* Just a dummy value */
659 sg_count = 1;
660 } else {
661 /* Just access the data directly from memory */
662 sg_count = dma_map_sg(mmc_dev(host->mmc),
663 data->sg, data->sg_len,
664 mmc_get_dma_dir(data));
665 }
666
667 if (sg_count == 0)
668 return -ENOSPC;
669
670 data->sg_count = sg_count;
671 data->host_cookie = cookie;
672
673 return sg_count;
674 }
675
sdhci_kmap_atomic(struct scatterlist * sg,unsigned long * flags)676 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
677 {
678 local_irq_save(*flags);
679 return kmap_atomic(sg_page(sg)) + sg->offset;
680 }
681
sdhci_kunmap_atomic(void * buffer,unsigned long * flags)682 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
683 {
684 kunmap_atomic(buffer);
685 local_irq_restore(*flags);
686 }
687
sdhci_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)688 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
689 dma_addr_t addr, int len, unsigned int cmd)
690 {
691 struct sdhci_adma2_64_desc *dma_desc = *desc;
692
693 /* 32-bit and 64-bit descriptors have these members in same position */
694 dma_desc->cmd = cpu_to_le16(cmd);
695 dma_desc->len = cpu_to_le16(len);
696 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
697
698 if (host->flags & SDHCI_USE_64_BIT_DMA)
699 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
700
701 *desc += host->desc_sz;
702 }
703 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
704
__sdhci_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)705 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
706 void **desc, dma_addr_t addr,
707 int len, unsigned int cmd)
708 {
709 if (host->ops->adma_write_desc)
710 host->ops->adma_write_desc(host, desc, addr, len, cmd);
711 else
712 sdhci_adma_write_desc(host, desc, addr, len, cmd);
713 }
714
sdhci_adma_mark_end(void * desc)715 static void sdhci_adma_mark_end(void *desc)
716 {
717 struct sdhci_adma2_64_desc *dma_desc = desc;
718
719 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
720 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
721 }
722
sdhci_adma_table_pre(struct sdhci_host * host,struct mmc_data * data,int sg_count)723 static void sdhci_adma_table_pre(struct sdhci_host *host,
724 struct mmc_data *data, int sg_count)
725 {
726 struct scatterlist *sg;
727 unsigned long flags;
728 dma_addr_t addr, align_addr;
729 void *desc, *align;
730 char *buffer;
731 int len, offset, i;
732
733 /*
734 * The spec does not specify endianness of descriptor table.
735 * We currently guess that it is LE.
736 */
737
738 host->sg_count = sg_count;
739
740 desc = host->adma_table;
741 align = host->align_buffer;
742
743 align_addr = host->align_addr;
744
745 for_each_sg(data->sg, sg, host->sg_count, i) {
746 addr = sg_dma_address(sg);
747 len = sg_dma_len(sg);
748
749 /*
750 * The SDHCI specification states that ADMA addresses must
751 * be 32-bit aligned. If they aren't, then we use a bounce
752 * buffer for the (up to three) bytes that screw up the
753 * alignment.
754 */
755 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
756 SDHCI_ADMA2_MASK;
757 if (offset) {
758 if (data->flags & MMC_DATA_WRITE) {
759 buffer = sdhci_kmap_atomic(sg, &flags);
760 memcpy(align, buffer, offset);
761 sdhci_kunmap_atomic(buffer, &flags);
762 }
763
764 /* tran, valid */
765 __sdhci_adma_write_desc(host, &desc, align_addr,
766 offset, ADMA2_TRAN_VALID);
767
768 BUG_ON(offset > 65536);
769
770 align += SDHCI_ADMA2_ALIGN;
771 align_addr += SDHCI_ADMA2_ALIGN;
772
773 addr += offset;
774 len -= offset;
775 }
776
777 BUG_ON(len > 65536);
778
779 /* tran, valid */
780 if (len)
781 __sdhci_adma_write_desc(host, &desc, addr, len,
782 ADMA2_TRAN_VALID);
783
784 /*
785 * If this triggers then we have a calculation bug
786 * somewhere. :/
787 */
788 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
789 }
790
791 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
792 /* Mark the last descriptor as the terminating descriptor */
793 if (desc != host->adma_table) {
794 desc -= host->desc_sz;
795 sdhci_adma_mark_end(desc);
796 }
797 } else {
798 /* Add a terminating entry - nop, end, valid */
799 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
800 }
801 }
802
sdhci_adma_table_post(struct sdhci_host * host,struct mmc_data * data)803 static void sdhci_adma_table_post(struct sdhci_host *host,
804 struct mmc_data *data)
805 {
806 struct scatterlist *sg;
807 int i, size;
808 void *align;
809 char *buffer;
810 unsigned long flags;
811
812 if (data->flags & MMC_DATA_READ) {
813 bool has_unaligned = false;
814
815 /* Do a quick scan of the SG list for any unaligned mappings */
816 for_each_sg(data->sg, sg, host->sg_count, i)
817 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
818 has_unaligned = true;
819 break;
820 }
821
822 if (has_unaligned) {
823 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
824 data->sg_len, DMA_FROM_DEVICE);
825
826 align = host->align_buffer;
827
828 for_each_sg(data->sg, sg, host->sg_count, i) {
829 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
830 size = SDHCI_ADMA2_ALIGN -
831 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
832
833 buffer = sdhci_kmap_atomic(sg, &flags);
834 memcpy(buffer, align, size);
835 sdhci_kunmap_atomic(buffer, &flags);
836
837 align += SDHCI_ADMA2_ALIGN;
838 }
839 }
840 }
841 }
842 }
843
sdhci_set_adma_addr(struct sdhci_host * host,dma_addr_t addr)844 static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
845 {
846 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
847 if (host->flags & SDHCI_USE_64_BIT_DMA)
848 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
849 }
850
sdhci_sdma_address(struct sdhci_host * host)851 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
852 {
853 if (host->bounce_buffer)
854 return host->bounce_addr;
855 else
856 return sg_dma_address(host->data->sg);
857 }
858
sdhci_set_sdma_addr(struct sdhci_host * host,dma_addr_t addr)859 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
860 {
861 if (host->v4_mode)
862 sdhci_set_adma_addr(host, addr);
863 else
864 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
865 }
866
sdhci_target_timeout(struct sdhci_host * host,struct mmc_command * cmd,struct mmc_data * data)867 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
868 struct mmc_command *cmd,
869 struct mmc_data *data)
870 {
871 unsigned int target_timeout;
872
873 /* timeout in us */
874 if (!data) {
875 target_timeout = cmd->busy_timeout * 1000;
876 } else {
877 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
878 if (host->clock && data->timeout_clks) {
879 unsigned long long val;
880
881 /*
882 * data->timeout_clks is in units of clock cycles.
883 * host->clock is in Hz. target_timeout is in us.
884 * Hence, us = 1000000 * cycles / Hz. Round up.
885 */
886 val = 1000000ULL * data->timeout_clks;
887 if (do_div(val, host->clock))
888 target_timeout++;
889 target_timeout += val;
890 }
891 }
892
893 return target_timeout;
894 }
895
sdhci_calc_sw_timeout(struct sdhci_host * host,struct mmc_command * cmd)896 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
897 struct mmc_command *cmd)
898 {
899 struct mmc_data *data = cmd->data;
900 struct mmc_host *mmc = host->mmc;
901 struct mmc_ios *ios = &mmc->ios;
902 unsigned char bus_width = 1 << ios->bus_width;
903 unsigned int blksz;
904 unsigned int freq;
905 u64 target_timeout;
906 u64 transfer_time;
907
908 target_timeout = sdhci_target_timeout(host, cmd, data);
909 target_timeout *= NSEC_PER_USEC;
910
911 if (data) {
912 blksz = data->blksz;
913 freq = host->mmc->actual_clock ? : host->clock;
914 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
915 do_div(transfer_time, freq);
916 /* multiply by '2' to account for any unknowns */
917 transfer_time = transfer_time * 2;
918 /* calculate timeout for the entire data */
919 host->data_timeout = data->blocks * target_timeout +
920 transfer_time;
921 } else {
922 host->data_timeout = target_timeout;
923 }
924
925 if (host->data_timeout)
926 host->data_timeout += MMC_CMD_TRANSFER_TIME;
927 }
928
sdhci_calc_timeout(struct sdhci_host * host,struct mmc_command * cmd,bool * too_big)929 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
930 bool *too_big)
931 {
932 u8 count;
933 struct mmc_data *data;
934 unsigned target_timeout, current_timeout;
935
936 *too_big = true;
937
938 /*
939 * If the host controller provides us with an incorrect timeout
940 * value, just skip the check and use 0xE. The hardware may take
941 * longer to time out, but that's much better than having a too-short
942 * timeout value.
943 */
944 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
945 return 0xE;
946
947 /* Unspecified command, asume max */
948 if (cmd == NULL)
949 return 0xE;
950
951 data = cmd->data;
952 /* Unspecified timeout, assume max */
953 if (!data && !cmd->busy_timeout)
954 return 0xE;
955
956 /* timeout in us */
957 target_timeout = sdhci_target_timeout(host, cmd, data);
958
959 /*
960 * Figure out needed cycles.
961 * We do this in steps in order to fit inside a 32 bit int.
962 * The first step is the minimum timeout, which will have a
963 * minimum resolution of 6 bits:
964 * (1) 2^13*1000 > 2^22,
965 * (2) host->timeout_clk < 2^16
966 * =>
967 * (1) / (2) > 2^6
968 */
969 count = 0;
970 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
971 while (current_timeout < target_timeout) {
972 count++;
973 current_timeout <<= 1;
974 if (count >= 0xF)
975 break;
976 }
977
978 if (count >= 0xF) {
979 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
980 DBG("Too large timeout 0x%x requested for CMD%d!\n",
981 count, cmd->opcode);
982 count = 0xE;
983 } else {
984 *too_big = false;
985 }
986
987 return count;
988 }
989
sdhci_set_transfer_irqs(struct sdhci_host * host)990 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
991 {
992 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
993 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
994
995 if (host->flags & SDHCI_REQ_USE_DMA)
996 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
997 else
998 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
999
1000 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1001 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1002 else
1003 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1004
1005 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1006 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1007 }
1008
sdhci_set_data_timeout_irq(struct sdhci_host * host,bool enable)1009 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1010 {
1011 if (enable)
1012 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1013 else
1014 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1015 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1016 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1017 }
1018 EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1019
__sdhci_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1020 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1021 {
1022 bool too_big = false;
1023 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1024
1025 if (too_big &&
1026 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1027 sdhci_calc_sw_timeout(host, cmd);
1028 sdhci_set_data_timeout_irq(host, false);
1029 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1030 sdhci_set_data_timeout_irq(host, true);
1031 }
1032
1033 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1034 }
1035 EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1036
sdhci_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1037 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1038 {
1039 if (host->ops->set_timeout)
1040 host->ops->set_timeout(host, cmd);
1041 else
1042 __sdhci_set_timeout(host, cmd);
1043 }
1044
sdhci_initialize_data(struct sdhci_host * host,struct mmc_data * data)1045 static void sdhci_initialize_data(struct sdhci_host *host,
1046 struct mmc_data *data)
1047 {
1048 WARN_ON(host->data);
1049
1050 /* Sanity checks */
1051 BUG_ON(data->blksz * data->blocks > 524288);
1052 BUG_ON(data->blksz > host->mmc->max_blk_size);
1053 BUG_ON(data->blocks > 65535);
1054
1055 host->data = data;
1056 host->data_early = 0;
1057 host->data->bytes_xfered = 0;
1058 }
1059
sdhci_set_block_info(struct sdhci_host * host,struct mmc_data * data)1060 static inline void sdhci_set_block_info(struct sdhci_host *host,
1061 struct mmc_data *data)
1062 {
1063 /* Set the DMA boundary value and block size */
1064 sdhci_writew(host,
1065 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1066 SDHCI_BLOCK_SIZE);
1067 /*
1068 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1069 * can be supported, in that case 16-bit block count register must be 0.
1070 */
1071 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1072 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1073 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1074 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1075 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1076 } else {
1077 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1078 }
1079 }
1080
sdhci_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)1081 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1082 {
1083 struct mmc_data *data = cmd->data;
1084
1085 sdhci_initialize_data(host, data);
1086
1087 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1088 struct scatterlist *sg;
1089 unsigned int length_mask, offset_mask;
1090 int i;
1091
1092 host->flags |= SDHCI_REQ_USE_DMA;
1093
1094 /*
1095 * FIXME: This doesn't account for merging when mapping the
1096 * scatterlist.
1097 *
1098 * The assumption here being that alignment and lengths are
1099 * the same after DMA mapping to device address space.
1100 */
1101 length_mask = 0;
1102 offset_mask = 0;
1103 if (host->flags & SDHCI_USE_ADMA) {
1104 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1105 length_mask = 3;
1106 /*
1107 * As we use up to 3 byte chunks to work
1108 * around alignment problems, we need to
1109 * check the offset as well.
1110 */
1111 offset_mask = 3;
1112 }
1113 } else {
1114 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1115 length_mask = 3;
1116 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1117 offset_mask = 3;
1118 }
1119
1120 if (unlikely(length_mask | offset_mask)) {
1121 for_each_sg(data->sg, sg, data->sg_len, i) {
1122 if (sg->length & length_mask) {
1123 DBG("Reverting to PIO because of transfer size (%d)\n",
1124 sg->length);
1125 host->flags &= ~SDHCI_REQ_USE_DMA;
1126 break;
1127 }
1128 if (sg->offset & offset_mask) {
1129 DBG("Reverting to PIO because of bad alignment\n");
1130 host->flags &= ~SDHCI_REQ_USE_DMA;
1131 break;
1132 }
1133 }
1134 }
1135 }
1136
1137 sdhci_config_dma(host);
1138
1139 if (host->flags & SDHCI_REQ_USE_DMA) {
1140 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1141
1142 if (sg_cnt <= 0) {
1143 /*
1144 * This only happens when someone fed
1145 * us an invalid request.
1146 */
1147 WARN_ON(1);
1148 host->flags &= ~SDHCI_REQ_USE_DMA;
1149 } else if (host->flags & SDHCI_USE_ADMA) {
1150 sdhci_adma_table_pre(host, data, sg_cnt);
1151 sdhci_set_adma_addr(host, host->adma_addr);
1152 } else {
1153 WARN_ON(sg_cnt != 1);
1154 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1155 }
1156 }
1157
1158 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1159 int flags;
1160
1161 flags = SG_MITER_ATOMIC;
1162 if (host->data->flags & MMC_DATA_READ)
1163 flags |= SG_MITER_TO_SG;
1164 else
1165 flags |= SG_MITER_FROM_SG;
1166 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1167 host->blocks = data->blocks;
1168 }
1169
1170 sdhci_set_transfer_irqs(host);
1171
1172 sdhci_set_block_info(host, data);
1173 }
1174
1175 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1176
sdhci_external_dma_init(struct sdhci_host * host)1177 static int sdhci_external_dma_init(struct sdhci_host *host)
1178 {
1179 int ret = 0;
1180 struct mmc_host *mmc = host->mmc;
1181
1182 host->tx_chan = dma_request_chan(mmc->parent, "tx");
1183 if (IS_ERR(host->tx_chan)) {
1184 ret = PTR_ERR(host->tx_chan);
1185 if (ret != -EPROBE_DEFER)
1186 pr_warn("Failed to request TX DMA channel.\n");
1187 host->tx_chan = NULL;
1188 return ret;
1189 }
1190
1191 host->rx_chan = dma_request_chan(mmc->parent, "rx");
1192 if (IS_ERR(host->rx_chan)) {
1193 if (host->tx_chan) {
1194 dma_release_channel(host->tx_chan);
1195 host->tx_chan = NULL;
1196 }
1197
1198 ret = PTR_ERR(host->rx_chan);
1199 if (ret != -EPROBE_DEFER)
1200 pr_warn("Failed to request RX DMA channel.\n");
1201 host->rx_chan = NULL;
1202 }
1203
1204 return ret;
1205 }
1206
sdhci_external_dma_channel(struct sdhci_host * host,struct mmc_data * data)1207 static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1208 struct mmc_data *data)
1209 {
1210 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1211 }
1212
sdhci_external_dma_setup(struct sdhci_host * host,struct mmc_command * cmd)1213 static int sdhci_external_dma_setup(struct sdhci_host *host,
1214 struct mmc_command *cmd)
1215 {
1216 int ret, i;
1217 enum dma_transfer_direction dir;
1218 struct dma_async_tx_descriptor *desc;
1219 struct mmc_data *data = cmd->data;
1220 struct dma_chan *chan;
1221 struct dma_slave_config cfg;
1222 dma_cookie_t cookie;
1223 int sg_cnt;
1224
1225 if (!host->mapbase)
1226 return -EINVAL;
1227
1228 memset(&cfg, 0, sizeof(cfg));
1229 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1230 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1231 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1232 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1233 cfg.src_maxburst = data->blksz / 4;
1234 cfg.dst_maxburst = data->blksz / 4;
1235
1236 /* Sanity check: all the SG entries must be aligned by block size. */
1237 for (i = 0; i < data->sg_len; i++) {
1238 if ((data->sg + i)->length % data->blksz)
1239 return -EINVAL;
1240 }
1241
1242 chan = sdhci_external_dma_channel(host, data);
1243
1244 ret = dmaengine_slave_config(chan, &cfg);
1245 if (ret)
1246 return ret;
1247
1248 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1249 if (sg_cnt <= 0)
1250 return -EINVAL;
1251
1252 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1253 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
1254 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1255 if (!desc)
1256 return -EINVAL;
1257
1258 desc->callback = NULL;
1259 desc->callback_param = NULL;
1260
1261 cookie = dmaengine_submit(desc);
1262 if (dma_submit_error(cookie))
1263 ret = cookie;
1264
1265 return ret;
1266 }
1267
sdhci_external_dma_release(struct sdhci_host * host)1268 static void sdhci_external_dma_release(struct sdhci_host *host)
1269 {
1270 if (host->tx_chan) {
1271 dma_release_channel(host->tx_chan);
1272 host->tx_chan = NULL;
1273 }
1274
1275 if (host->rx_chan) {
1276 dma_release_channel(host->rx_chan);
1277 host->rx_chan = NULL;
1278 }
1279
1280 sdhci_switch_external_dma(host, false);
1281 }
1282
__sdhci_external_dma_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)1283 static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1284 struct mmc_command *cmd)
1285 {
1286 struct mmc_data *data = cmd->data;
1287
1288 sdhci_initialize_data(host, data);
1289
1290 host->flags |= SDHCI_REQ_USE_DMA;
1291 sdhci_set_transfer_irqs(host);
1292
1293 sdhci_set_block_info(host, data);
1294 }
1295
sdhci_external_dma_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)1296 static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1297 struct mmc_command *cmd)
1298 {
1299 if (!sdhci_external_dma_setup(host, cmd)) {
1300 __sdhci_external_dma_prepare_data(host, cmd);
1301 } else {
1302 sdhci_external_dma_release(host);
1303 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1304 mmc_hostname(host->mmc));
1305 sdhci_prepare_data(host, cmd);
1306 }
1307 }
1308
sdhci_external_dma_pre_transfer(struct sdhci_host * host,struct mmc_command * cmd)1309 static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1310 struct mmc_command *cmd)
1311 {
1312 struct dma_chan *chan;
1313
1314 if (!cmd->data)
1315 return;
1316
1317 chan = sdhci_external_dma_channel(host, cmd->data);
1318 if (chan)
1319 dma_async_issue_pending(chan);
1320 }
1321
1322 #else
1323
sdhci_external_dma_init(struct sdhci_host * host)1324 static inline int sdhci_external_dma_init(struct sdhci_host *host)
1325 {
1326 return -EOPNOTSUPP;
1327 }
1328
sdhci_external_dma_release(struct sdhci_host * host)1329 static inline void sdhci_external_dma_release(struct sdhci_host *host)
1330 {
1331 }
1332
sdhci_external_dma_prepare_data(struct sdhci_host * host,struct mmc_command * cmd)1333 static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1334 struct mmc_command *cmd)
1335 {
1336 /* This should never happen */
1337 WARN_ON_ONCE(1);
1338 }
1339
sdhci_external_dma_pre_transfer(struct sdhci_host * host,struct mmc_command * cmd)1340 static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1341 struct mmc_command *cmd)
1342 {
1343 }
1344
sdhci_external_dma_channel(struct sdhci_host * host,struct mmc_data * data)1345 static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1346 struct mmc_data *data)
1347 {
1348 return NULL;
1349 }
1350
1351 #endif
1352
sdhci_switch_external_dma(struct sdhci_host * host,bool en)1353 void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1354 {
1355 host->use_external_dma = en;
1356 }
1357 EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1358
sdhci_auto_cmd12(struct sdhci_host * host,struct mmc_request * mrq)1359 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1360 struct mmc_request *mrq)
1361 {
1362 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1363 !mrq->cap_cmd_during_tfr;
1364 }
1365
sdhci_auto_cmd23(struct sdhci_host * host,struct mmc_request * mrq)1366 static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1367 struct mmc_request *mrq)
1368 {
1369 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1370 }
1371
sdhci_manual_cmd23(struct sdhci_host * host,struct mmc_request * mrq)1372 static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1373 struct mmc_request *mrq)
1374 {
1375 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1376 }
1377
sdhci_auto_cmd_select(struct sdhci_host * host,struct mmc_command * cmd,u16 * mode)1378 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1379 struct mmc_command *cmd,
1380 u16 *mode)
1381 {
1382 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1383 (cmd->opcode != SD_IO_RW_EXTENDED);
1384 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1385 u16 ctrl2;
1386
1387 /*
1388 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1389 * Select' is recommended rather than use of 'Auto CMD12
1390 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1391 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
1392 */
1393 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1394 (use_cmd12 || use_cmd23)) {
1395 *mode |= SDHCI_TRNS_AUTO_SEL;
1396
1397 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1398 if (use_cmd23)
1399 ctrl2 |= SDHCI_CMD23_ENABLE;
1400 else
1401 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1402 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1403
1404 return;
1405 }
1406
1407 /*
1408 * If we are sending CMD23, CMD12 never gets sent
1409 * on successful completion (so no Auto-CMD12).
1410 */
1411 if (use_cmd12)
1412 *mode |= SDHCI_TRNS_AUTO_CMD12;
1413 else if (use_cmd23)
1414 *mode |= SDHCI_TRNS_AUTO_CMD23;
1415 }
1416
sdhci_set_transfer_mode(struct sdhci_host * host,struct mmc_command * cmd)1417 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1418 struct mmc_command *cmd)
1419 {
1420 u16 mode = 0;
1421 struct mmc_data *data = cmd->data;
1422
1423 if (data == NULL) {
1424 if (host->quirks2 &
1425 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1426 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1427 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1428 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1429 } else {
1430 /* clear Auto CMD settings for no data CMDs */
1431 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1432 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1433 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1434 }
1435 return;
1436 }
1437
1438 WARN_ON(!host->data);
1439
1440 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1441 mode = SDHCI_TRNS_BLK_CNT_EN;
1442
1443 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1444 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1445 sdhci_auto_cmd_select(host, cmd, &mode);
1446 if (sdhci_auto_cmd23(host, cmd->mrq))
1447 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1448 }
1449
1450 if (data->flags & MMC_DATA_READ)
1451 mode |= SDHCI_TRNS_READ;
1452 if (host->flags & SDHCI_REQ_USE_DMA)
1453 mode |= SDHCI_TRNS_DMA;
1454
1455 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1456 }
1457
sdhci_needs_reset(struct sdhci_host * host,struct mmc_request * mrq)1458 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1459 {
1460 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1461 ((mrq->cmd && mrq->cmd->error) ||
1462 (mrq->sbc && mrq->sbc->error) ||
1463 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1464 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1465 }
1466
sdhci_set_mrq_done(struct sdhci_host * host,struct mmc_request * mrq)1467 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1468 {
1469 int i;
1470
1471 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1472 if (host->mrqs_done[i] == mrq) {
1473 WARN_ON(1);
1474 return;
1475 }
1476 }
1477
1478 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1479 if (!host->mrqs_done[i]) {
1480 host->mrqs_done[i] = mrq;
1481 break;
1482 }
1483 }
1484
1485 WARN_ON(i >= SDHCI_MAX_MRQS);
1486 }
1487
__sdhci_finish_mrq(struct sdhci_host * host,struct mmc_request * mrq)1488 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1489 {
1490 if (host->cmd && host->cmd->mrq == mrq)
1491 host->cmd = NULL;
1492
1493 if (host->data_cmd && host->data_cmd->mrq == mrq)
1494 host->data_cmd = NULL;
1495
1496 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1497 host->deferred_cmd = NULL;
1498
1499 if (host->data && host->data->mrq == mrq)
1500 host->data = NULL;
1501
1502 if (sdhci_needs_reset(host, mrq))
1503 host->pending_reset = true;
1504
1505 sdhci_set_mrq_done(host, mrq);
1506
1507 sdhci_del_timer(host, mrq);
1508
1509 if (!sdhci_has_requests(host))
1510 sdhci_led_deactivate(host);
1511 }
1512
sdhci_finish_mrq(struct sdhci_host * host,struct mmc_request * mrq)1513 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1514 {
1515 __sdhci_finish_mrq(host, mrq);
1516
1517 queue_work(host->complete_wq, &host->complete_work);
1518 }
1519
__sdhci_finish_data(struct sdhci_host * host,bool sw_data_timeout)1520 static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1521 {
1522 struct mmc_command *data_cmd = host->data_cmd;
1523 struct mmc_data *data = host->data;
1524
1525 host->data = NULL;
1526 host->data_cmd = NULL;
1527
1528 /*
1529 * The controller needs a reset of internal state machines upon error
1530 * conditions.
1531 */
1532 if (data->error) {
1533 if (!host->cmd || host->cmd == data_cmd)
1534 sdhci_do_reset(host, SDHCI_RESET_CMD);
1535 sdhci_do_reset(host, SDHCI_RESET_DATA);
1536 }
1537
1538 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1539 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1540 sdhci_adma_table_post(host, data);
1541
1542 /*
1543 * The specification states that the block count register must
1544 * be updated, but it does not specify at what point in the
1545 * data flow. That makes the register entirely useless to read
1546 * back so we have to assume that nothing made it to the card
1547 * in the event of an error.
1548 */
1549 if (data->error)
1550 data->bytes_xfered = 0;
1551 else
1552 data->bytes_xfered = data->blksz * data->blocks;
1553
1554 /*
1555 * Need to send CMD12 if -
1556 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1557 * b) error in multiblock transfer
1558 */
1559 if (data->stop &&
1560 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1561 data->error)) {
1562 /*
1563 * 'cap_cmd_during_tfr' request must not use the command line
1564 * after mmc_command_done() has been called. It is upper layer's
1565 * responsibility to send the stop command if required.
1566 */
1567 if (data->mrq->cap_cmd_during_tfr) {
1568 __sdhci_finish_mrq(host, data->mrq);
1569 } else {
1570 /* Avoid triggering warning in sdhci_send_command() */
1571 host->cmd = NULL;
1572 if (!sdhci_send_command(host, data->stop)) {
1573 if (sw_data_timeout) {
1574 /*
1575 * This is anyway a sw data timeout, so
1576 * give up now.
1577 */
1578 data->stop->error = -EIO;
1579 __sdhci_finish_mrq(host, data->mrq);
1580 } else {
1581 WARN_ON(host->deferred_cmd);
1582 host->deferred_cmd = data->stop;
1583 }
1584 }
1585 }
1586 } else {
1587 __sdhci_finish_mrq(host, data->mrq);
1588 }
1589 }
1590
sdhci_finish_data(struct sdhci_host * host)1591 static void sdhci_finish_data(struct sdhci_host *host)
1592 {
1593 __sdhci_finish_data(host, false);
1594 }
1595
sdhci_send_command(struct sdhci_host * host,struct mmc_command * cmd)1596 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1597 {
1598 int flags;
1599 u32 mask;
1600 unsigned long timeout;
1601
1602 WARN_ON(host->cmd);
1603
1604 /* Initially, a command has no error */
1605 cmd->error = 0;
1606
1607 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1608 cmd->opcode == MMC_STOP_TRANSMISSION)
1609 cmd->flags |= MMC_RSP_BUSY;
1610
1611 mask = SDHCI_CMD_INHIBIT;
1612 if (sdhci_data_line_cmd(cmd))
1613 mask |= SDHCI_DATA_INHIBIT;
1614
1615 /* We shouldn't wait for data inihibit for stop commands, even
1616 though they might use busy signaling */
1617 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1618 mask &= ~SDHCI_DATA_INHIBIT;
1619
1620 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1621 return false;
1622
1623 host->cmd = cmd;
1624 host->data_timeout = 0;
1625 if (sdhci_data_line_cmd(cmd)) {
1626 WARN_ON(host->data_cmd);
1627 host->data_cmd = cmd;
1628 sdhci_set_timeout(host, cmd);
1629 }
1630
1631 if (cmd->data) {
1632 if (host->use_external_dma)
1633 sdhci_external_dma_prepare_data(host, cmd);
1634 else
1635 sdhci_prepare_data(host, cmd);
1636 }
1637
1638 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1639
1640 sdhci_set_transfer_mode(host, cmd);
1641
1642 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1643 WARN_ONCE(1, "Unsupported response type!\n");
1644 /*
1645 * This does not happen in practice because 136-bit response
1646 * commands never have busy waiting, so rather than complicate
1647 * the error path, just remove busy waiting and continue.
1648 */
1649 cmd->flags &= ~MMC_RSP_BUSY;
1650 }
1651
1652 if (!(cmd->flags & MMC_RSP_PRESENT))
1653 flags = SDHCI_CMD_RESP_NONE;
1654 else if (cmd->flags & MMC_RSP_136)
1655 flags = SDHCI_CMD_RESP_LONG;
1656 else if (cmd->flags & MMC_RSP_BUSY)
1657 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1658 else
1659 flags = SDHCI_CMD_RESP_SHORT;
1660
1661 if (cmd->flags & MMC_RSP_CRC)
1662 flags |= SDHCI_CMD_CRC;
1663 if (cmd->flags & MMC_RSP_OPCODE)
1664 flags |= SDHCI_CMD_INDEX;
1665
1666 /* CMD19 is special in that the Data Present Select should be set */
1667 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1668 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1669 flags |= SDHCI_CMD_DATA;
1670
1671 timeout = jiffies;
1672 if (host->data_timeout)
1673 timeout += nsecs_to_jiffies(host->data_timeout);
1674 else if (!cmd->data && cmd->busy_timeout > 9000)
1675 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1676 else
1677 timeout += 10 * HZ;
1678 sdhci_mod_timer(host, cmd->mrq, timeout);
1679
1680 if (host->use_external_dma)
1681 sdhci_external_dma_pre_transfer(host, cmd);
1682
1683 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1684
1685 return true;
1686 }
1687
sdhci_present_error(struct sdhci_host * host,struct mmc_command * cmd,bool present)1688 static bool sdhci_present_error(struct sdhci_host *host,
1689 struct mmc_command *cmd, bool present)
1690 {
1691 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1692 cmd->error = -ENOMEDIUM;
1693 return true;
1694 }
1695
1696 return false;
1697 }
1698
sdhci_send_command_retry(struct sdhci_host * host,struct mmc_command * cmd,unsigned long flags)1699 static bool sdhci_send_command_retry(struct sdhci_host *host,
1700 struct mmc_command *cmd,
1701 unsigned long flags)
1702 __releases(host->lock)
1703 __acquires(host->lock)
1704 {
1705 struct mmc_command *deferred_cmd = host->deferred_cmd;
1706 int timeout = 10; /* Approx. 10 ms */
1707 bool present;
1708
1709 while (!sdhci_send_command(host, cmd)) {
1710 if (!timeout--) {
1711 pr_err("%s: Controller never released inhibit bit(s).\n",
1712 mmc_hostname(host->mmc));
1713 sdhci_dumpregs(host);
1714 cmd->error = -EIO;
1715 return false;
1716 }
1717
1718 spin_unlock_irqrestore(&host->lock, flags);
1719
1720 usleep_range(1000, 1250);
1721
1722 present = host->mmc->ops->get_cd(host->mmc);
1723
1724 spin_lock_irqsave(&host->lock, flags);
1725
1726 /* A deferred command might disappear, handle that */
1727 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1728 return true;
1729
1730 if (sdhci_present_error(host, cmd, present))
1731 return false;
1732 }
1733
1734 if (cmd == host->deferred_cmd)
1735 host->deferred_cmd = NULL;
1736
1737 return true;
1738 }
1739
sdhci_read_rsp_136(struct sdhci_host * host,struct mmc_command * cmd)1740 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1741 {
1742 int i, reg;
1743
1744 for (i = 0; i < 4; i++) {
1745 reg = SDHCI_RESPONSE + (3 - i) * 4;
1746 cmd->resp[i] = sdhci_readl(host, reg);
1747 }
1748
1749 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1750 return;
1751
1752 /* CRC is stripped so we need to do some shifting */
1753 for (i = 0; i < 4; i++) {
1754 cmd->resp[i] <<= 8;
1755 if (i != 3)
1756 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1757 }
1758 }
1759
sdhci_finish_command(struct sdhci_host * host)1760 static void sdhci_finish_command(struct sdhci_host *host)
1761 {
1762 struct mmc_command *cmd = host->cmd;
1763
1764 host->cmd = NULL;
1765
1766 if (cmd->flags & MMC_RSP_PRESENT) {
1767 if (cmd->flags & MMC_RSP_136) {
1768 sdhci_read_rsp_136(host, cmd);
1769 } else {
1770 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1771 }
1772 }
1773
1774 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1775 mmc_command_done(host->mmc, cmd->mrq);
1776
1777 /*
1778 * The host can send and interrupt when the busy state has
1779 * ended, allowing us to wait without wasting CPU cycles.
1780 * The busy signal uses DAT0 so this is similar to waiting
1781 * for data to complete.
1782 *
1783 * Note: The 1.0 specification is a bit ambiguous about this
1784 * feature so there might be some problems with older
1785 * controllers.
1786 */
1787 if (cmd->flags & MMC_RSP_BUSY) {
1788 if (cmd->data) {
1789 DBG("Cannot wait for busy signal when also doing a data transfer");
1790 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1791 cmd == host->data_cmd) {
1792 /* Command complete before busy is ended */
1793 return;
1794 }
1795 }
1796
1797 /* Finished CMD23, now send actual command. */
1798 if (cmd == cmd->mrq->sbc) {
1799 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1800 WARN_ON(host->deferred_cmd);
1801 host->deferred_cmd = cmd->mrq->cmd;
1802 }
1803 } else {
1804
1805 /* Processed actual command. */
1806 if (host->data && host->data_early)
1807 sdhci_finish_data(host);
1808
1809 if (!cmd->data)
1810 __sdhci_finish_mrq(host, cmd->mrq);
1811 }
1812 }
1813
sdhci_get_preset_value(struct sdhci_host * host)1814 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1815 {
1816 u16 preset = 0;
1817
1818 switch (host->timing) {
1819 case MMC_TIMING_MMC_HS:
1820 case MMC_TIMING_SD_HS:
1821 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1822 break;
1823 case MMC_TIMING_UHS_SDR12:
1824 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1825 break;
1826 case MMC_TIMING_UHS_SDR25:
1827 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1828 break;
1829 case MMC_TIMING_UHS_SDR50:
1830 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1831 break;
1832 case MMC_TIMING_UHS_SDR104:
1833 case MMC_TIMING_MMC_HS200:
1834 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1835 break;
1836 case MMC_TIMING_UHS_DDR50:
1837 case MMC_TIMING_MMC_DDR52:
1838 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1839 break;
1840 case MMC_TIMING_MMC_HS400:
1841 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1842 break;
1843 default:
1844 pr_warn("%s: Invalid UHS-I mode selected\n",
1845 mmc_hostname(host->mmc));
1846 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1847 break;
1848 }
1849 return preset;
1850 }
1851
sdhci_calc_clk(struct sdhci_host * host,unsigned int clock,unsigned int * actual_clock)1852 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1853 unsigned int *actual_clock)
1854 {
1855 int div = 0; /* Initialized for compiler warning */
1856 int real_div = div, clk_mul = 1;
1857 u16 clk = 0;
1858 bool switch_base_clk = false;
1859
1860 if (host->version >= SDHCI_SPEC_300) {
1861 if (host->preset_enabled) {
1862 u16 pre_val;
1863
1864 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1865 pre_val = sdhci_get_preset_value(host);
1866 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1867 if (host->clk_mul &&
1868 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1869 clk = SDHCI_PROG_CLOCK_MODE;
1870 real_div = div + 1;
1871 clk_mul = host->clk_mul;
1872 } else {
1873 real_div = max_t(int, 1, div << 1);
1874 }
1875 goto clock_set;
1876 }
1877
1878 /*
1879 * Check if the Host Controller supports Programmable Clock
1880 * Mode.
1881 */
1882 if (host->clk_mul) {
1883 for (div = 1; div <= 1024; div++) {
1884 if ((host->max_clk * host->clk_mul / div)
1885 <= clock)
1886 break;
1887 }
1888 if ((host->max_clk * host->clk_mul / div) <= clock) {
1889 /*
1890 * Set Programmable Clock Mode in the Clock
1891 * Control register.
1892 */
1893 clk = SDHCI_PROG_CLOCK_MODE;
1894 real_div = div;
1895 clk_mul = host->clk_mul;
1896 div--;
1897 } else {
1898 /*
1899 * Divisor can be too small to reach clock
1900 * speed requirement. Then use the base clock.
1901 */
1902 switch_base_clk = true;
1903 }
1904 }
1905
1906 if (!host->clk_mul || switch_base_clk) {
1907 /* Version 3.00 divisors must be a multiple of 2. */
1908 if (host->max_clk <= clock)
1909 div = 1;
1910 else {
1911 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1912 div += 2) {
1913 if ((host->max_clk / div) <= clock)
1914 break;
1915 }
1916 }
1917 real_div = div;
1918 div >>= 1;
1919 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1920 && !div && host->max_clk <= 25000000)
1921 div = 1;
1922 }
1923 } else {
1924 /* Version 2.00 divisors must be a power of 2. */
1925 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1926 if ((host->max_clk / div) <= clock)
1927 break;
1928 }
1929 real_div = div;
1930 div >>= 1;
1931 }
1932
1933 clock_set:
1934 if (real_div)
1935 *actual_clock = (host->max_clk * clk_mul) / real_div;
1936 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1937 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1938 << SDHCI_DIVIDER_HI_SHIFT;
1939
1940 return clk;
1941 }
1942 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1943
sdhci_enable_clk(struct sdhci_host * host,u16 clk)1944 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1945 {
1946 ktime_t timeout;
1947
1948 clk |= SDHCI_CLOCK_INT_EN;
1949 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1950
1951 /* Wait max 150 ms */
1952 timeout = ktime_add_ms(ktime_get(), 150);
1953 while (1) {
1954 bool timedout = ktime_after(ktime_get(), timeout);
1955
1956 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1957 if (clk & SDHCI_CLOCK_INT_STABLE)
1958 break;
1959 if (timedout) {
1960 pr_err("%s: Internal clock never stabilised.\n",
1961 mmc_hostname(host->mmc));
1962 sdhci_dumpregs(host);
1963 return;
1964 }
1965 udelay(10);
1966 }
1967
1968 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1969 clk |= SDHCI_CLOCK_PLL_EN;
1970 clk &= ~SDHCI_CLOCK_INT_STABLE;
1971 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1972
1973 /* Wait max 150 ms */
1974 timeout = ktime_add_ms(ktime_get(), 150);
1975 while (1) {
1976 bool timedout = ktime_after(ktime_get(), timeout);
1977
1978 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1979 if (clk & SDHCI_CLOCK_INT_STABLE)
1980 break;
1981 if (timedout) {
1982 pr_err("%s: PLL clock never stabilised.\n",
1983 mmc_hostname(host->mmc));
1984 sdhci_dumpregs(host);
1985 return;
1986 }
1987 udelay(10);
1988 }
1989 }
1990
1991 clk |= SDHCI_CLOCK_CARD_EN;
1992 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1993 }
1994 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1995
sdhci_set_clock(struct sdhci_host * host,unsigned int clock)1996 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1997 {
1998 u16 clk;
1999
2000 host->mmc->actual_clock = 0;
2001
2002 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2003
2004 if (clock == 0)
2005 return;
2006
2007 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2008 sdhci_enable_clk(host, clk);
2009 }
2010 EXPORT_SYMBOL_GPL(sdhci_set_clock);
2011
sdhci_set_power_reg(struct sdhci_host * host,unsigned char mode,unsigned short vdd)2012 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2013 unsigned short vdd)
2014 {
2015 struct mmc_host *mmc = host->mmc;
2016
2017 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2018
2019 if (mode != MMC_POWER_OFF)
2020 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2021 else
2022 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2023 }
2024
sdhci_set_power_noreg(struct sdhci_host * host,unsigned char mode,unsigned short vdd)2025 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2026 unsigned short vdd)
2027 {
2028 u8 pwr = 0;
2029
2030 if (mode != MMC_POWER_OFF) {
2031 switch (1 << vdd) {
2032 case MMC_VDD_165_195:
2033 /*
2034 * Without a regulator, SDHCI does not support 2.0v
2035 * so we only get here if the driver deliberately
2036 * added the 2.0v range to ocr_avail. Map it to 1.8v
2037 * for the purpose of turning on the power.
2038 */
2039 case MMC_VDD_20_21:
2040 pwr = SDHCI_POWER_180;
2041 break;
2042 case MMC_VDD_29_30:
2043 case MMC_VDD_30_31:
2044 pwr = SDHCI_POWER_300;
2045 break;
2046 case MMC_VDD_32_33:
2047 case MMC_VDD_33_34:
2048 /*
2049 * 3.4 ~ 3.6V are valid only for those platforms where it's
2050 * known that the voltage range is supported by hardware.
2051 */
2052 case MMC_VDD_34_35:
2053 case MMC_VDD_35_36:
2054 pwr = SDHCI_POWER_330;
2055 break;
2056 default:
2057 WARN(1, "%s: Invalid vdd %#x\n",
2058 mmc_hostname(host->mmc), vdd);
2059 break;
2060 }
2061 }
2062
2063 if (host->pwr == pwr)
2064 return;
2065
2066 host->pwr = pwr;
2067
2068 if (pwr == 0) {
2069 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2070 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2071 sdhci_runtime_pm_bus_off(host);
2072 } else {
2073 /*
2074 * Spec says that we should clear the power reg before setting
2075 * a new value. Some controllers don't seem to like this though.
2076 */
2077 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2078 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2079
2080 /*
2081 * At least the Marvell CaFe chip gets confused if we set the
2082 * voltage and set turn on power at the same time, so set the
2083 * voltage first.
2084 */
2085 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2086 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2087
2088 pwr |= SDHCI_POWER_ON;
2089
2090 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2091
2092 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2093 sdhci_runtime_pm_bus_on(host);
2094
2095 /*
2096 * Some controllers need an extra 10ms delay of 10ms before
2097 * they can apply clock after applying power
2098 */
2099 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2100 mdelay(10);
2101 }
2102 }
2103 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2104
sdhci_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)2105 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2106 unsigned short vdd)
2107 {
2108 if (IS_ERR(host->mmc->supply.vmmc))
2109 sdhci_set_power_noreg(host, mode, vdd);
2110 else
2111 sdhci_set_power_reg(host, mode, vdd);
2112 }
2113 EXPORT_SYMBOL_GPL(sdhci_set_power);
2114
2115 /*
2116 * Some controllers need to configure a valid bus voltage on their power
2117 * register regardless of whether an external regulator is taking care of power
2118 * supply. This helper function takes care of it if set as the controller's
2119 * sdhci_ops.set_power callback.
2120 */
sdhci_set_power_and_bus_voltage(struct sdhci_host * host,unsigned char mode,unsigned short vdd)2121 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2122 unsigned char mode,
2123 unsigned short vdd)
2124 {
2125 if (!IS_ERR(host->mmc->supply.vmmc)) {
2126 struct mmc_host *mmc = host->mmc;
2127
2128 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2129 }
2130 sdhci_set_power_noreg(host, mode, vdd);
2131 }
2132 EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2133
2134 /*****************************************************************************\
2135 * *
2136 * MMC callbacks *
2137 * *
2138 \*****************************************************************************/
2139
sdhci_request(struct mmc_host * mmc,struct mmc_request * mrq)2140 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2141 {
2142 struct sdhci_host *host = mmc_priv(mmc);
2143 struct mmc_command *cmd;
2144 unsigned long flags;
2145 bool present;
2146
2147 /* Firstly check card presence */
2148 present = mmc->ops->get_cd(mmc);
2149
2150 spin_lock_irqsave(&host->lock, flags);
2151
2152 sdhci_led_activate(host);
2153
2154 if (sdhci_present_error(host, mrq->cmd, present))
2155 goto out_finish;
2156
2157 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2158
2159 if (!sdhci_send_command_retry(host, cmd, flags))
2160 goto out_finish;
2161
2162 spin_unlock_irqrestore(&host->lock, flags);
2163
2164 return;
2165
2166 out_finish:
2167 sdhci_finish_mrq(host, mrq);
2168 spin_unlock_irqrestore(&host->lock, flags);
2169 }
2170 EXPORT_SYMBOL_GPL(sdhci_request);
2171
sdhci_request_atomic(struct mmc_host * mmc,struct mmc_request * mrq)2172 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2173 {
2174 struct sdhci_host *host = mmc_priv(mmc);
2175 struct mmc_command *cmd;
2176 unsigned long flags;
2177 int ret = 0;
2178
2179 spin_lock_irqsave(&host->lock, flags);
2180
2181 if (sdhci_present_error(host, mrq->cmd, true)) {
2182 sdhci_finish_mrq(host, mrq);
2183 goto out_finish;
2184 }
2185
2186 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2187
2188 /*
2189 * The HSQ may send a command in interrupt context without polling
2190 * the busy signaling, which means we should return BUSY if controller
2191 * has not released inhibit bits to allow HSQ trying to send request
2192 * again in non-atomic context. So we should not finish this request
2193 * here.
2194 */
2195 if (!sdhci_send_command(host, cmd))
2196 ret = -EBUSY;
2197 else
2198 sdhci_led_activate(host);
2199
2200 out_finish:
2201 spin_unlock_irqrestore(&host->lock, flags);
2202 return ret;
2203 }
2204 EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2205
sdhci_set_bus_width(struct sdhci_host * host,int width)2206 void sdhci_set_bus_width(struct sdhci_host *host, int width)
2207 {
2208 u8 ctrl;
2209
2210 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2211 if (width == MMC_BUS_WIDTH_8) {
2212 ctrl &= ~SDHCI_CTRL_4BITBUS;
2213 ctrl |= SDHCI_CTRL_8BITBUS;
2214 } else {
2215 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2216 ctrl &= ~SDHCI_CTRL_8BITBUS;
2217 if (width == MMC_BUS_WIDTH_4)
2218 ctrl |= SDHCI_CTRL_4BITBUS;
2219 else
2220 ctrl &= ~SDHCI_CTRL_4BITBUS;
2221 }
2222 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2223 }
2224 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2225
sdhci_set_uhs_signaling(struct sdhci_host * host,unsigned timing)2226 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2227 {
2228 u16 ctrl_2;
2229
2230 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2231 /* Select Bus Speed Mode for host */
2232 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2233 if ((timing == MMC_TIMING_MMC_HS200) ||
2234 (timing == MMC_TIMING_UHS_SDR104))
2235 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2236 else if (timing == MMC_TIMING_UHS_SDR12)
2237 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2238 else if (timing == MMC_TIMING_UHS_SDR25)
2239 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2240 else if (timing == MMC_TIMING_UHS_SDR50)
2241 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2242 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2243 (timing == MMC_TIMING_MMC_DDR52))
2244 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2245 else if (timing == MMC_TIMING_MMC_HS400)
2246 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2247 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2248 }
2249 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2250
sdhci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)2251 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2252 {
2253 struct sdhci_host *host = mmc_priv(mmc);
2254 u8 ctrl;
2255
2256 if (ios->power_mode == MMC_POWER_UNDEFINED)
2257 return;
2258
2259 if (host->flags & SDHCI_DEVICE_DEAD) {
2260 if (!IS_ERR(mmc->supply.vmmc) &&
2261 ios->power_mode == MMC_POWER_OFF)
2262 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2263 return;
2264 }
2265
2266 /*
2267 * Reset the chip on each power off.
2268 * Should clear out any weird states.
2269 */
2270 if (ios->power_mode == MMC_POWER_OFF) {
2271 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2272 sdhci_reinit(host);
2273 }
2274
2275 if (host->version >= SDHCI_SPEC_300 &&
2276 (ios->power_mode == MMC_POWER_UP) &&
2277 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2278 sdhci_enable_preset_value(host, false);
2279
2280 if (!ios->clock || ios->clock != host->clock) {
2281 host->ops->set_clock(host, ios->clock);
2282 host->clock = ios->clock;
2283
2284 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2285 host->clock) {
2286 host->timeout_clk = host->mmc->actual_clock ?
2287 host->mmc->actual_clock / 1000 :
2288 host->clock / 1000;
2289 host->mmc->max_busy_timeout =
2290 host->ops->get_max_timeout_count ?
2291 host->ops->get_max_timeout_count(host) :
2292 1 << 27;
2293 host->mmc->max_busy_timeout /= host->timeout_clk;
2294 }
2295 }
2296
2297 if (host->ops->set_power)
2298 host->ops->set_power(host, ios->power_mode, ios->vdd);
2299 else
2300 sdhci_set_power(host, ios->power_mode, ios->vdd);
2301
2302 if (host->ops->platform_send_init_74_clocks)
2303 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2304
2305 host->ops->set_bus_width(host, ios->bus_width);
2306
2307 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2308
2309 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2310 if (ios->timing == MMC_TIMING_SD_HS ||
2311 ios->timing == MMC_TIMING_MMC_HS ||
2312 ios->timing == MMC_TIMING_MMC_HS400 ||
2313 ios->timing == MMC_TIMING_MMC_HS200 ||
2314 ios->timing == MMC_TIMING_MMC_DDR52 ||
2315 ios->timing == MMC_TIMING_UHS_SDR50 ||
2316 ios->timing == MMC_TIMING_UHS_SDR104 ||
2317 ios->timing == MMC_TIMING_UHS_DDR50 ||
2318 ios->timing == MMC_TIMING_UHS_SDR25)
2319 ctrl |= SDHCI_CTRL_HISPD;
2320 else
2321 ctrl &= ~SDHCI_CTRL_HISPD;
2322 }
2323
2324 if (host->version >= SDHCI_SPEC_300) {
2325 u16 clk, ctrl_2;
2326
2327 if (!host->preset_enabled) {
2328 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2329 /*
2330 * We only need to set Driver Strength if the
2331 * preset value enable is not set.
2332 */
2333 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2334 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2335 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2336 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2337 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2338 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2339 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2340 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2341 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2342 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2343 else {
2344 pr_warn("%s: invalid driver type, default to driver type B\n",
2345 mmc_hostname(mmc));
2346 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2347 }
2348
2349 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2350 } else {
2351 /*
2352 * According to SDHC Spec v3.00, if the Preset Value
2353 * Enable in the Host Control 2 register is set, we
2354 * need to reset SD Clock Enable before changing High
2355 * Speed Enable to avoid generating clock gliches.
2356 */
2357
2358 /* Reset SD Clock Enable */
2359 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2360 clk &= ~SDHCI_CLOCK_CARD_EN;
2361 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2362
2363 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2364
2365 /* Re-enable SD Clock */
2366 host->ops->set_clock(host, host->clock);
2367 }
2368
2369 /* Reset SD Clock Enable */
2370 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2371 clk &= ~SDHCI_CLOCK_CARD_EN;
2372 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2373
2374 host->ops->set_uhs_signaling(host, ios->timing);
2375 host->timing = ios->timing;
2376
2377 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2378 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2379 (ios->timing == MMC_TIMING_UHS_SDR25) ||
2380 (ios->timing == MMC_TIMING_UHS_SDR50) ||
2381 (ios->timing == MMC_TIMING_UHS_SDR104) ||
2382 (ios->timing == MMC_TIMING_UHS_DDR50) ||
2383 (ios->timing == MMC_TIMING_MMC_DDR52))) {
2384 u16 preset;
2385
2386 sdhci_enable_preset_value(host, true);
2387 preset = sdhci_get_preset_value(host);
2388 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2389 preset);
2390 }
2391
2392 /* Re-enable SD Clock */
2393 host->ops->set_clock(host, host->clock);
2394 } else
2395 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2396
2397 /*
2398 * Some (ENE) controllers go apeshit on some ios operation,
2399 * signalling timeout and CRC errors even on CMD0. Resetting
2400 * it on each ios seems to solve the problem.
2401 */
2402 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2403 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2404 }
2405 EXPORT_SYMBOL_GPL(sdhci_set_ios);
2406
sdhci_get_cd(struct mmc_host * mmc)2407 static int sdhci_get_cd(struct mmc_host *mmc)
2408 {
2409 struct sdhci_host *host = mmc_priv(mmc);
2410 int gpio_cd = mmc_gpio_get_cd(mmc);
2411 bool allow = true;
2412
2413 if (host->flags & SDHCI_DEVICE_DEAD)
2414 return 0;
2415
2416 /* If nonremovable, assume that the card is always present. */
2417 if (!mmc_card_is_removable(host->mmc))
2418 return 1;
2419
2420 trace_android_vh_sdhci_get_cd(host, &allow);
2421 if (!allow)
2422 return 0;
2423
2424 /*
2425 * Try slot gpio detect, if defined it take precedence
2426 * over build in controller functionality
2427 */
2428 if (gpio_cd >= 0)
2429 return !!gpio_cd;
2430
2431 /* If polling, assume that the card is always present. */
2432 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2433 return 1;
2434
2435 /* Host native card detect */
2436 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2437 }
2438
sdhci_check_ro(struct sdhci_host * host)2439 static int sdhci_check_ro(struct sdhci_host *host)
2440 {
2441 unsigned long flags;
2442 int is_readonly;
2443
2444 spin_lock_irqsave(&host->lock, flags);
2445
2446 if (host->flags & SDHCI_DEVICE_DEAD)
2447 is_readonly = 0;
2448 else if (host->ops->get_ro)
2449 is_readonly = host->ops->get_ro(host);
2450 else if (mmc_can_gpio_ro(host->mmc))
2451 is_readonly = mmc_gpio_get_ro(host->mmc);
2452 else
2453 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2454 & SDHCI_WRITE_PROTECT);
2455
2456 spin_unlock_irqrestore(&host->lock, flags);
2457
2458 /* This quirk needs to be replaced by a callback-function later */
2459 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2460 !is_readonly : is_readonly;
2461 }
2462
2463 #define SAMPLE_COUNT 5
2464
sdhci_get_ro(struct mmc_host * mmc)2465 static int sdhci_get_ro(struct mmc_host *mmc)
2466 {
2467 struct sdhci_host *host = mmc_priv(mmc);
2468 int i, ro_count;
2469
2470 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2471 return sdhci_check_ro(host);
2472
2473 ro_count = 0;
2474 for (i = 0; i < SAMPLE_COUNT; i++) {
2475 if (sdhci_check_ro(host)) {
2476 if (++ro_count > SAMPLE_COUNT / 2)
2477 return 1;
2478 }
2479 msleep(30);
2480 }
2481 return 0;
2482 }
2483
sdhci_hw_reset(struct mmc_host * mmc)2484 static void sdhci_hw_reset(struct mmc_host *mmc)
2485 {
2486 struct sdhci_host *host = mmc_priv(mmc);
2487
2488 if (host->ops && host->ops->hw_reset)
2489 host->ops->hw_reset(host);
2490 }
2491
sdhci_enable_sdio_irq_nolock(struct sdhci_host * host,int enable)2492 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2493 {
2494 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2495 if (enable)
2496 host->ier |= SDHCI_INT_CARD_INT;
2497 else
2498 host->ier &= ~SDHCI_INT_CARD_INT;
2499
2500 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2501 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2502 }
2503 }
2504
sdhci_enable_sdio_irq(struct mmc_host * mmc,int enable)2505 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2506 {
2507 struct sdhci_host *host = mmc_priv(mmc);
2508 unsigned long flags;
2509
2510 if (enable)
2511 pm_runtime_get_noresume(host->mmc->parent);
2512
2513 spin_lock_irqsave(&host->lock, flags);
2514 sdhci_enable_sdio_irq_nolock(host, enable);
2515 spin_unlock_irqrestore(&host->lock, flags);
2516
2517 if (!enable)
2518 pm_runtime_put_noidle(host->mmc->parent);
2519 }
2520 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2521
sdhci_ack_sdio_irq(struct mmc_host * mmc)2522 static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2523 {
2524 struct sdhci_host *host = mmc_priv(mmc);
2525 unsigned long flags;
2526
2527 spin_lock_irqsave(&host->lock, flags);
2528 sdhci_enable_sdio_irq_nolock(host, true);
2529 spin_unlock_irqrestore(&host->lock, flags);
2530 }
2531
sdhci_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)2532 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2533 struct mmc_ios *ios)
2534 {
2535 struct sdhci_host *host = mmc_priv(mmc);
2536 u16 ctrl;
2537 int ret;
2538
2539 /*
2540 * Signal Voltage Switching is only applicable for Host Controllers
2541 * v3.00 and above.
2542 */
2543 if (host->version < SDHCI_SPEC_300)
2544 return 0;
2545
2546 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2547
2548 switch (ios->signal_voltage) {
2549 case MMC_SIGNAL_VOLTAGE_330:
2550 if (!(host->flags & SDHCI_SIGNALING_330))
2551 return -EINVAL;
2552 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2553 ctrl &= ~SDHCI_CTRL_VDD_180;
2554 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2555
2556 if (!IS_ERR(mmc->supply.vqmmc)) {
2557 ret = mmc_regulator_set_vqmmc(mmc, ios);
2558 if (ret < 0) {
2559 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2560 mmc_hostname(mmc));
2561 return -EIO;
2562 }
2563 }
2564 /* Wait for 5ms */
2565 usleep_range(5000, 5500);
2566
2567 /* 3.3V regulator output should be stable within 5 ms */
2568 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2569 if (!(ctrl & SDHCI_CTRL_VDD_180))
2570 return 0;
2571
2572 pr_warn("%s: 3.3V regulator output did not become stable\n",
2573 mmc_hostname(mmc));
2574
2575 return -EAGAIN;
2576 case MMC_SIGNAL_VOLTAGE_180:
2577 if (!(host->flags & SDHCI_SIGNALING_180))
2578 return -EINVAL;
2579 if (!IS_ERR(mmc->supply.vqmmc)) {
2580 ret = mmc_regulator_set_vqmmc(mmc, ios);
2581 if (ret < 0) {
2582 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2583 mmc_hostname(mmc));
2584 return -EIO;
2585 }
2586 }
2587
2588 /*
2589 * Enable 1.8V Signal Enable in the Host Control2
2590 * register
2591 */
2592 ctrl |= SDHCI_CTRL_VDD_180;
2593 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2594
2595 /* Some controller need to do more when switching */
2596 if (host->ops->voltage_switch)
2597 host->ops->voltage_switch(host);
2598
2599 /* 1.8V regulator output should be stable within 5 ms */
2600 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2601 if (ctrl & SDHCI_CTRL_VDD_180)
2602 return 0;
2603
2604 pr_warn("%s: 1.8V regulator output did not become stable\n",
2605 mmc_hostname(mmc));
2606
2607 return -EAGAIN;
2608 case MMC_SIGNAL_VOLTAGE_120:
2609 if (!(host->flags & SDHCI_SIGNALING_120))
2610 return -EINVAL;
2611 if (!IS_ERR(mmc->supply.vqmmc)) {
2612 ret = mmc_regulator_set_vqmmc(mmc, ios);
2613 if (ret < 0) {
2614 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2615 mmc_hostname(mmc));
2616 return -EIO;
2617 }
2618 }
2619 return 0;
2620 default:
2621 /* No signal voltage switch required */
2622 return 0;
2623 }
2624 }
2625 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2626
sdhci_card_busy(struct mmc_host * mmc)2627 static int sdhci_card_busy(struct mmc_host *mmc)
2628 {
2629 struct sdhci_host *host = mmc_priv(mmc);
2630 u32 present_state;
2631
2632 /* Check whether DAT[0] is 0 */
2633 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2634
2635 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2636 }
2637
sdhci_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2638 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2639 {
2640 struct sdhci_host *host = mmc_priv(mmc);
2641 unsigned long flags;
2642
2643 spin_lock_irqsave(&host->lock, flags);
2644 host->flags |= SDHCI_HS400_TUNING;
2645 spin_unlock_irqrestore(&host->lock, flags);
2646
2647 return 0;
2648 }
2649
sdhci_start_tuning(struct sdhci_host * host)2650 void sdhci_start_tuning(struct sdhci_host *host)
2651 {
2652 u16 ctrl;
2653
2654 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2655 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2656 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2657 ctrl |= SDHCI_CTRL_TUNED_CLK;
2658 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2659
2660 /*
2661 * As per the Host Controller spec v3.00, tuning command
2662 * generates Buffer Read Ready interrupt, so enable that.
2663 *
2664 * Note: The spec clearly says that when tuning sequence
2665 * is being performed, the controller does not generate
2666 * interrupts other than Buffer Read Ready interrupt. But
2667 * to make sure we don't hit a controller bug, we _only_
2668 * enable Buffer Read Ready interrupt here.
2669 */
2670 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2671 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2672 }
2673 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2674
sdhci_end_tuning(struct sdhci_host * host)2675 void sdhci_end_tuning(struct sdhci_host *host)
2676 {
2677 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2678 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2679 }
2680 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2681
sdhci_reset_tuning(struct sdhci_host * host)2682 void sdhci_reset_tuning(struct sdhci_host *host)
2683 {
2684 u16 ctrl;
2685
2686 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2687 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2688 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2689 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2690 }
2691 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2692
sdhci_abort_tuning(struct sdhci_host * host,u32 opcode)2693 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2694 {
2695 sdhci_reset_tuning(host);
2696
2697 sdhci_do_reset(host, SDHCI_RESET_CMD);
2698 sdhci_do_reset(host, SDHCI_RESET_DATA);
2699
2700 sdhci_end_tuning(host);
2701
2702 mmc_abort_tuning(host->mmc, opcode);
2703 }
2704 EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2705
2706 /*
2707 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2708 * tuning command does not have a data payload (or rather the hardware does it
2709 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2710 * interrupt setup is different to other commands and there is no timeout
2711 * interrupt so special handling is needed.
2712 */
sdhci_send_tuning(struct sdhci_host * host,u32 opcode)2713 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2714 {
2715 struct mmc_host *mmc = host->mmc;
2716 struct mmc_command cmd = {};
2717 struct mmc_request mrq = {};
2718 unsigned long flags;
2719 u32 b = host->sdma_boundary;
2720
2721 spin_lock_irqsave(&host->lock, flags);
2722
2723 cmd.opcode = opcode;
2724 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2725 cmd.mrq = &mrq;
2726
2727 mrq.cmd = &cmd;
2728 /*
2729 * In response to CMD19, the card sends 64 bytes of tuning
2730 * block to the Host Controller. So we set the block size
2731 * to 64 here.
2732 */
2733 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2734 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2735 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2736 else
2737 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2738
2739 /*
2740 * The tuning block is sent by the card to the host controller.
2741 * So we set the TRNS_READ bit in the Transfer Mode register.
2742 * This also takes care of setting DMA Enable and Multi Block
2743 * Select in the same register to 0.
2744 */
2745 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2746
2747 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2748 spin_unlock_irqrestore(&host->lock, flags);
2749 host->tuning_done = 0;
2750 return;
2751 }
2752
2753 host->cmd = NULL;
2754
2755 sdhci_del_timer(host, &mrq);
2756
2757 host->tuning_done = 0;
2758
2759 spin_unlock_irqrestore(&host->lock, flags);
2760
2761 /* Wait for Buffer Read Ready interrupt */
2762 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2763 msecs_to_jiffies(50));
2764
2765 }
2766 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2767
__sdhci_execute_tuning(struct sdhci_host * host,u32 opcode)2768 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2769 {
2770 int i;
2771
2772 /*
2773 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2774 * of loops reaches tuning loop count.
2775 */
2776 for (i = 0; i < host->tuning_loop_count; i++) {
2777 u16 ctrl;
2778
2779 sdhci_send_tuning(host, opcode);
2780
2781 if (!host->tuning_done) {
2782 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2783 mmc_hostname(host->mmc));
2784 sdhci_abort_tuning(host, opcode);
2785 return -ETIMEDOUT;
2786 }
2787
2788 /* Spec does not require a delay between tuning cycles */
2789 if (host->tuning_delay > 0)
2790 mdelay(host->tuning_delay);
2791
2792 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2793 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2794 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2795 return 0; /* Success! */
2796 break;
2797 }
2798
2799 }
2800
2801 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2802 mmc_hostname(host->mmc));
2803 sdhci_reset_tuning(host);
2804 return -EAGAIN;
2805 }
2806
sdhci_execute_tuning(struct mmc_host * mmc,u32 opcode)2807 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2808 {
2809 struct sdhci_host *host = mmc_priv(mmc);
2810 int err = 0;
2811 unsigned int tuning_count = 0;
2812 bool hs400_tuning;
2813
2814 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2815
2816 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2817 tuning_count = host->tuning_count;
2818
2819 /*
2820 * The Host Controller needs tuning in case of SDR104 and DDR50
2821 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2822 * the Capabilities register.
2823 * If the Host Controller supports the HS200 mode then the
2824 * tuning function has to be executed.
2825 */
2826 switch (host->timing) {
2827 /* HS400 tuning is done in HS200 mode */
2828 case MMC_TIMING_MMC_HS400:
2829 err = -EINVAL;
2830 goto out;
2831
2832 case MMC_TIMING_MMC_HS200:
2833 /*
2834 * Periodic re-tuning for HS400 is not expected to be needed, so
2835 * disable it here.
2836 */
2837 if (hs400_tuning)
2838 tuning_count = 0;
2839 break;
2840
2841 case MMC_TIMING_UHS_SDR104:
2842 case MMC_TIMING_UHS_DDR50:
2843 break;
2844
2845 case MMC_TIMING_UHS_SDR50:
2846 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2847 break;
2848 fallthrough;
2849
2850 default:
2851 goto out;
2852 }
2853
2854 if (host->ops->platform_execute_tuning) {
2855 err = host->ops->platform_execute_tuning(host, opcode);
2856 goto out;
2857 }
2858
2859 host->mmc->retune_period = tuning_count;
2860
2861 if (host->tuning_delay < 0)
2862 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2863
2864 sdhci_start_tuning(host);
2865
2866 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2867
2868 sdhci_end_tuning(host);
2869 out:
2870 host->flags &= ~SDHCI_HS400_TUNING;
2871
2872 return err;
2873 }
2874 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2875
sdhci_enable_preset_value(struct sdhci_host * host,bool enable)2876 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2877 {
2878 /* Host Controller v3.00 defines preset value registers */
2879 if (host->version < SDHCI_SPEC_300)
2880 return;
2881
2882 /*
2883 * We only enable or disable Preset Value if they are not already
2884 * enabled or disabled respectively. Otherwise, we bail out.
2885 */
2886 if (host->preset_enabled != enable) {
2887 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2888
2889 if (enable)
2890 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2891 else
2892 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2893
2894 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2895
2896 if (enable)
2897 host->flags |= SDHCI_PV_ENABLED;
2898 else
2899 host->flags &= ~SDHCI_PV_ENABLED;
2900
2901 host->preset_enabled = enable;
2902 }
2903 }
2904
sdhci_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)2905 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2906 int err)
2907 {
2908 struct sdhci_host *host = mmc_priv(mmc);
2909 struct mmc_data *data = mrq->data;
2910
2911 if (data->host_cookie != COOKIE_UNMAPPED)
2912 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2913 mmc_get_dma_dir(data));
2914
2915 data->host_cookie = COOKIE_UNMAPPED;
2916 }
2917
sdhci_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)2918 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2919 {
2920 struct sdhci_host *host = mmc_priv(mmc);
2921
2922 mrq->data->host_cookie = COOKIE_UNMAPPED;
2923
2924 /*
2925 * No pre-mapping in the pre hook if we're using the bounce buffer,
2926 * for that we would need two bounce buffers since one buffer is
2927 * in flight when this is getting called.
2928 */
2929 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2930 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2931 }
2932
sdhci_error_out_mrqs(struct sdhci_host * host,int err)2933 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2934 {
2935 if (host->data_cmd) {
2936 host->data_cmd->error = err;
2937 sdhci_finish_mrq(host, host->data_cmd->mrq);
2938 }
2939
2940 if (host->cmd) {
2941 host->cmd->error = err;
2942 sdhci_finish_mrq(host, host->cmd->mrq);
2943 }
2944 }
2945
sdhci_card_event(struct mmc_host * mmc)2946 static void sdhci_card_event(struct mmc_host *mmc)
2947 {
2948 struct sdhci_host *host = mmc_priv(mmc);
2949 unsigned long flags;
2950 int present;
2951
2952 /* First check if client has provided their own card event */
2953 if (host->ops->card_event)
2954 host->ops->card_event(host);
2955
2956 present = mmc->ops->get_cd(mmc);
2957
2958 spin_lock_irqsave(&host->lock, flags);
2959
2960 /* Check sdhci_has_requests() first in case we are runtime suspended */
2961 if (sdhci_has_requests(host) && !present) {
2962 pr_err("%s: Card removed during transfer!\n",
2963 mmc_hostname(host->mmc));
2964 pr_err("%s: Resetting controller.\n",
2965 mmc_hostname(host->mmc));
2966
2967 sdhci_do_reset(host, SDHCI_RESET_CMD);
2968 sdhci_do_reset(host, SDHCI_RESET_DATA);
2969
2970 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2971 }
2972
2973 spin_unlock_irqrestore(&host->lock, flags);
2974 }
2975
2976 static const struct mmc_host_ops sdhci_ops = {
2977 .request = sdhci_request,
2978 .post_req = sdhci_post_req,
2979 .pre_req = sdhci_pre_req,
2980 .set_ios = sdhci_set_ios,
2981 .get_cd = sdhci_get_cd,
2982 .get_ro = sdhci_get_ro,
2983 .hw_reset = sdhci_hw_reset,
2984 .enable_sdio_irq = sdhci_enable_sdio_irq,
2985 .ack_sdio_irq = sdhci_ack_sdio_irq,
2986 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2987 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2988 .execute_tuning = sdhci_execute_tuning,
2989 .card_event = sdhci_card_event,
2990 .card_busy = sdhci_card_busy,
2991 };
2992
2993 /*****************************************************************************\
2994 * *
2995 * Request done *
2996 * *
2997 \*****************************************************************************/
2998
sdhci_request_done(struct sdhci_host * host)2999 static bool sdhci_request_done(struct sdhci_host *host)
3000 {
3001 unsigned long flags;
3002 struct mmc_request *mrq;
3003 int i;
3004
3005 spin_lock_irqsave(&host->lock, flags);
3006
3007 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3008 mrq = host->mrqs_done[i];
3009 if (mrq)
3010 break;
3011 }
3012
3013 if (!mrq) {
3014 spin_unlock_irqrestore(&host->lock, flags);
3015 return true;
3016 }
3017
3018 /*
3019 * The controller needs a reset of internal state machines
3020 * upon error conditions.
3021 */
3022 if (sdhci_needs_reset(host, mrq)) {
3023 /*
3024 * Do not finish until command and data lines are available for
3025 * reset. Note there can only be one other mrq, so it cannot
3026 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3027 * would both be null.
3028 */
3029 if (host->cmd || host->data_cmd) {
3030 spin_unlock_irqrestore(&host->lock, flags);
3031 return true;
3032 }
3033
3034 /* Some controllers need this kick or reset won't work here */
3035 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3036 /* This is to force an update */
3037 host->ops->set_clock(host, host->clock);
3038
3039 /*
3040 * Spec says we should do both at the same time, but Ricoh
3041 * controllers do not like that.
3042 */
3043 sdhci_do_reset(host, SDHCI_RESET_CMD);
3044 sdhci_do_reset(host, SDHCI_RESET_DATA);
3045
3046 host->pending_reset = false;
3047 }
3048
3049 /*
3050 * Always unmap the data buffers if they were mapped by
3051 * sdhci_prepare_data() whenever we finish with a request.
3052 * This avoids leaking DMA mappings on error.
3053 */
3054 if (host->flags & SDHCI_REQ_USE_DMA) {
3055 struct mmc_data *data = mrq->data;
3056
3057 if (host->use_external_dma && data &&
3058 (mrq->cmd->error || data->error)) {
3059 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3060
3061 host->mrqs_done[i] = NULL;
3062 spin_unlock_irqrestore(&host->lock, flags);
3063 dmaengine_terminate_sync(chan);
3064 spin_lock_irqsave(&host->lock, flags);
3065 sdhci_set_mrq_done(host, mrq);
3066 }
3067
3068 if (data && data->host_cookie == COOKIE_MAPPED) {
3069 if (host->bounce_buffer) {
3070 /*
3071 * On reads, copy the bounced data into the
3072 * sglist
3073 */
3074 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3075 unsigned int length = data->bytes_xfered;
3076
3077 if (length > host->bounce_buffer_size) {
3078 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3079 mmc_hostname(host->mmc),
3080 host->bounce_buffer_size,
3081 data->bytes_xfered);
3082 /* Cap it down and continue */
3083 length = host->bounce_buffer_size;
3084 }
3085 dma_sync_single_for_cpu(
3086 host->mmc->parent,
3087 host->bounce_addr,
3088 host->bounce_buffer_size,
3089 DMA_FROM_DEVICE);
3090 sg_copy_from_buffer(data->sg,
3091 data->sg_len,
3092 host->bounce_buffer,
3093 length);
3094 } else {
3095 /* No copying, just switch ownership */
3096 dma_sync_single_for_cpu(
3097 host->mmc->parent,
3098 host->bounce_addr,
3099 host->bounce_buffer_size,
3100 mmc_get_dma_dir(data));
3101 }
3102 } else {
3103 /* Unmap the raw data */
3104 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3105 data->sg_len,
3106 mmc_get_dma_dir(data));
3107 }
3108 data->host_cookie = COOKIE_UNMAPPED;
3109 }
3110 }
3111
3112 host->mrqs_done[i] = NULL;
3113
3114 spin_unlock_irqrestore(&host->lock, flags);
3115
3116 if (host->ops->request_done)
3117 host->ops->request_done(host, mrq);
3118 else
3119 mmc_request_done(host->mmc, mrq);
3120
3121 return false;
3122 }
3123
sdhci_complete_work(struct work_struct * work)3124 static void sdhci_complete_work(struct work_struct *work)
3125 {
3126 struct sdhci_host *host = container_of(work, struct sdhci_host,
3127 complete_work);
3128
3129 while (!sdhci_request_done(host))
3130 ;
3131 }
3132
sdhci_timeout_timer(struct timer_list * t)3133 static void sdhci_timeout_timer(struct timer_list *t)
3134 {
3135 struct sdhci_host *host;
3136 unsigned long flags;
3137
3138 host = from_timer(host, t, timer);
3139
3140 spin_lock_irqsave(&host->lock, flags);
3141
3142 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3143 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3144 mmc_hostname(host->mmc));
3145 sdhci_dumpregs(host);
3146
3147 host->cmd->error = -ETIMEDOUT;
3148 sdhci_finish_mrq(host, host->cmd->mrq);
3149 }
3150
3151 spin_unlock_irqrestore(&host->lock, flags);
3152 }
3153
sdhci_timeout_data_timer(struct timer_list * t)3154 static void sdhci_timeout_data_timer(struct timer_list *t)
3155 {
3156 struct sdhci_host *host;
3157 unsigned long flags;
3158
3159 host = from_timer(host, t, data_timer);
3160
3161 spin_lock_irqsave(&host->lock, flags);
3162
3163 if (host->data || host->data_cmd ||
3164 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3165 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3166 mmc_hostname(host->mmc));
3167 sdhci_dumpregs(host);
3168
3169 if (host->data) {
3170 host->data->error = -ETIMEDOUT;
3171 __sdhci_finish_data(host, true);
3172 queue_work(host->complete_wq, &host->complete_work);
3173 } else if (host->data_cmd) {
3174 host->data_cmd->error = -ETIMEDOUT;
3175 sdhci_finish_mrq(host, host->data_cmd->mrq);
3176 } else {
3177 host->cmd->error = -ETIMEDOUT;
3178 sdhci_finish_mrq(host, host->cmd->mrq);
3179 }
3180 }
3181
3182 spin_unlock_irqrestore(&host->lock, flags);
3183 }
3184
3185 /*****************************************************************************\
3186 * *
3187 * Interrupt handling *
3188 * *
3189 \*****************************************************************************/
3190
sdhci_cmd_irq(struct sdhci_host * host,u32 intmask,u32 * intmask_p)3191 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3192 {
3193 /* Handle auto-CMD12 error */
3194 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3195 struct mmc_request *mrq = host->data_cmd->mrq;
3196 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3197 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3198 SDHCI_INT_DATA_TIMEOUT :
3199 SDHCI_INT_DATA_CRC;
3200
3201 /* Treat auto-CMD12 error the same as data error */
3202 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3203 *intmask_p |= data_err_bit;
3204 return;
3205 }
3206 }
3207
3208 if (!host->cmd) {
3209 /*
3210 * SDHCI recovers from errors by resetting the cmd and data
3211 * circuits. Until that is done, there very well might be more
3212 * interrupts, so ignore them in that case.
3213 */
3214 if (host->pending_reset)
3215 return;
3216 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3217 mmc_hostname(host->mmc), (unsigned)intmask);
3218 sdhci_dumpregs(host);
3219 return;
3220 }
3221
3222 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3223 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3224 if (intmask & SDHCI_INT_TIMEOUT)
3225 host->cmd->error = -ETIMEDOUT;
3226 else
3227 host->cmd->error = -EILSEQ;
3228
3229 /* Treat data command CRC error the same as data CRC error */
3230 if (host->cmd->data &&
3231 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3232 SDHCI_INT_CRC) {
3233 host->cmd = NULL;
3234 *intmask_p |= SDHCI_INT_DATA_CRC;
3235 return;
3236 }
3237
3238 __sdhci_finish_mrq(host, host->cmd->mrq);
3239 return;
3240 }
3241
3242 /* Handle auto-CMD23 error */
3243 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3244 struct mmc_request *mrq = host->cmd->mrq;
3245 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3246 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3247 -ETIMEDOUT :
3248 -EILSEQ;
3249
3250 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3251 mrq->sbc->error = err;
3252 __sdhci_finish_mrq(host, mrq);
3253 return;
3254 }
3255 }
3256
3257 if (intmask & SDHCI_INT_RESPONSE)
3258 sdhci_finish_command(host);
3259 }
3260
sdhci_adma_show_error(struct sdhci_host * host)3261 static void sdhci_adma_show_error(struct sdhci_host *host)
3262 {
3263 void *desc = host->adma_table;
3264 dma_addr_t dma = host->adma_addr;
3265
3266 sdhci_dumpregs(host);
3267
3268 while (true) {
3269 struct sdhci_adma2_64_desc *dma_desc = desc;
3270
3271 if (host->flags & SDHCI_USE_64_BIT_DMA)
3272 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3273 (unsigned long long)dma,
3274 le32_to_cpu(dma_desc->addr_hi),
3275 le32_to_cpu(dma_desc->addr_lo),
3276 le16_to_cpu(dma_desc->len),
3277 le16_to_cpu(dma_desc->cmd));
3278 else
3279 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3280 (unsigned long long)dma,
3281 le32_to_cpu(dma_desc->addr_lo),
3282 le16_to_cpu(dma_desc->len),
3283 le16_to_cpu(dma_desc->cmd));
3284
3285 desc += host->desc_sz;
3286 dma += host->desc_sz;
3287
3288 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3289 break;
3290 }
3291 }
3292
sdhci_data_irq(struct sdhci_host * host,u32 intmask)3293 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3294 {
3295 u32 command;
3296
3297 /* CMD19 generates _only_ Buffer Read Ready interrupt */
3298 if (intmask & SDHCI_INT_DATA_AVAIL) {
3299 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3300 if (command == MMC_SEND_TUNING_BLOCK ||
3301 command == MMC_SEND_TUNING_BLOCK_HS200) {
3302 host->tuning_done = 1;
3303 wake_up(&host->buf_ready_int);
3304 return;
3305 }
3306 }
3307
3308 if (!host->data) {
3309 struct mmc_command *data_cmd = host->data_cmd;
3310
3311 /*
3312 * The "data complete" interrupt is also used to
3313 * indicate that a busy state has ended. See comment
3314 * above in sdhci_cmd_irq().
3315 */
3316 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3317 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3318 host->data_cmd = NULL;
3319 data_cmd->error = -ETIMEDOUT;
3320 __sdhci_finish_mrq(host, data_cmd->mrq);
3321 return;
3322 }
3323 if (intmask & SDHCI_INT_DATA_END) {
3324 host->data_cmd = NULL;
3325 /*
3326 * Some cards handle busy-end interrupt
3327 * before the command completed, so make
3328 * sure we do things in the proper order.
3329 */
3330 if (host->cmd == data_cmd)
3331 return;
3332
3333 __sdhci_finish_mrq(host, data_cmd->mrq);
3334 return;
3335 }
3336 }
3337
3338 /*
3339 * SDHCI recovers from errors by resetting the cmd and data
3340 * circuits. Until that is done, there very well might be more
3341 * interrupts, so ignore them in that case.
3342 */
3343 if (host->pending_reset)
3344 return;
3345
3346 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3347 mmc_hostname(host->mmc), (unsigned)intmask);
3348 sdhci_dumpregs(host);
3349
3350 return;
3351 }
3352
3353 if (intmask & SDHCI_INT_DATA_TIMEOUT)
3354 host->data->error = -ETIMEDOUT;
3355 else if (intmask & SDHCI_INT_DATA_END_BIT)
3356 host->data->error = -EILSEQ;
3357 else if ((intmask & SDHCI_INT_DATA_CRC) &&
3358 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3359 != MMC_BUS_TEST_R)
3360 host->data->error = -EILSEQ;
3361 else if (intmask & SDHCI_INT_ADMA_ERROR) {
3362 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3363 intmask);
3364 sdhci_adma_show_error(host);
3365 host->data->error = -EIO;
3366 if (host->ops->adma_workaround)
3367 host->ops->adma_workaround(host, intmask);
3368 }
3369
3370 if (host->data->error)
3371 sdhci_finish_data(host);
3372 else {
3373 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3374 sdhci_transfer_pio(host);
3375
3376 /*
3377 * We currently don't do anything fancy with DMA
3378 * boundaries, but as we can't disable the feature
3379 * we need to at least restart the transfer.
3380 *
3381 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3382 * should return a valid address to continue from, but as
3383 * some controllers are faulty, don't trust them.
3384 */
3385 if (intmask & SDHCI_INT_DMA_END) {
3386 dma_addr_t dmastart, dmanow;
3387
3388 dmastart = sdhci_sdma_address(host);
3389 dmanow = dmastart + host->data->bytes_xfered;
3390 /*
3391 * Force update to the next DMA block boundary.
3392 */
3393 dmanow = (dmanow &
3394 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3395 SDHCI_DEFAULT_BOUNDARY_SIZE;
3396 host->data->bytes_xfered = dmanow - dmastart;
3397 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3398 &dmastart, host->data->bytes_xfered, &dmanow);
3399 sdhci_set_sdma_addr(host, dmanow);
3400 }
3401
3402 if (intmask & SDHCI_INT_DATA_END) {
3403 if (host->cmd == host->data_cmd) {
3404 /*
3405 * Data managed to finish before the
3406 * command completed. Make sure we do
3407 * things in the proper order.
3408 */
3409 host->data_early = 1;
3410 } else {
3411 sdhci_finish_data(host);
3412 }
3413 }
3414 }
3415 }
3416
sdhci_defer_done(struct sdhci_host * host,struct mmc_request * mrq)3417 static inline bool sdhci_defer_done(struct sdhci_host *host,
3418 struct mmc_request *mrq)
3419 {
3420 struct mmc_data *data = mrq->data;
3421
3422 return host->pending_reset || host->always_defer_done ||
3423 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3424 data->host_cookie == COOKIE_MAPPED);
3425 }
3426
sdhci_irq(int irq,void * dev_id)3427 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3428 {
3429 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3430 irqreturn_t result = IRQ_NONE;
3431 struct sdhci_host *host = dev_id;
3432 u32 intmask, mask, unexpected = 0;
3433 int max_loops = 16;
3434 int i;
3435
3436 spin_lock(&host->lock);
3437
3438 if (host->runtime_suspended) {
3439 spin_unlock(&host->lock);
3440 return IRQ_NONE;
3441 }
3442
3443 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3444 if (!intmask || intmask == 0xffffffff) {
3445 result = IRQ_NONE;
3446 goto out;
3447 }
3448
3449 do {
3450 DBG("IRQ status 0x%08x\n", intmask);
3451
3452 if (host->ops->irq) {
3453 intmask = host->ops->irq(host, intmask);
3454 if (!intmask)
3455 goto cont;
3456 }
3457
3458 /* Clear selected interrupts. */
3459 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3460 SDHCI_INT_BUS_POWER);
3461 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3462
3463 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3464 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3465 SDHCI_CARD_PRESENT;
3466
3467 /*
3468 * There is a observation on i.mx esdhc. INSERT
3469 * bit will be immediately set again when it gets
3470 * cleared, if a card is inserted. We have to mask
3471 * the irq to prevent interrupt storm which will
3472 * freeze the system. And the REMOVE gets the
3473 * same situation.
3474 *
3475 * More testing are needed here to ensure it works
3476 * for other platforms though.
3477 */
3478 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3479 SDHCI_INT_CARD_REMOVE);
3480 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3481 SDHCI_INT_CARD_INSERT;
3482 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3483 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3484
3485 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3486 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3487
3488 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3489 SDHCI_INT_CARD_REMOVE);
3490 result = IRQ_WAKE_THREAD;
3491 }
3492
3493 if (intmask & SDHCI_INT_CMD_MASK)
3494 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3495
3496 if (intmask & SDHCI_INT_DATA_MASK)
3497 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3498
3499 if (intmask & SDHCI_INT_BUS_POWER)
3500 pr_err("%s: Card is consuming too much power!\n",
3501 mmc_hostname(host->mmc));
3502
3503 if (intmask & SDHCI_INT_RETUNE)
3504 mmc_retune_needed(host->mmc);
3505
3506 if ((intmask & SDHCI_INT_CARD_INT) &&
3507 (host->ier & SDHCI_INT_CARD_INT)) {
3508 sdhci_enable_sdio_irq_nolock(host, false);
3509 sdio_signal_irq(host->mmc);
3510 }
3511
3512 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3513 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3514 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3515 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3516
3517 if (intmask) {
3518 unexpected |= intmask;
3519 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3520 }
3521 cont:
3522 if (result == IRQ_NONE)
3523 result = IRQ_HANDLED;
3524
3525 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3526 } while (intmask && --max_loops);
3527
3528 /* Determine if mrqs can be completed immediately */
3529 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3530 struct mmc_request *mrq = host->mrqs_done[i];
3531
3532 if (!mrq)
3533 continue;
3534
3535 if (sdhci_defer_done(host, mrq)) {
3536 result = IRQ_WAKE_THREAD;
3537 } else {
3538 mrqs_done[i] = mrq;
3539 host->mrqs_done[i] = NULL;
3540 }
3541 }
3542 out:
3543 if (host->deferred_cmd)
3544 result = IRQ_WAKE_THREAD;
3545
3546 spin_unlock(&host->lock);
3547
3548 /* Process mrqs ready for immediate completion */
3549 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3550 if (!mrqs_done[i])
3551 continue;
3552
3553 if (host->ops->request_done)
3554 host->ops->request_done(host, mrqs_done[i]);
3555 else
3556 mmc_request_done(host->mmc, mrqs_done[i]);
3557 }
3558
3559 if (unexpected) {
3560 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3561 mmc_hostname(host->mmc), unexpected);
3562 sdhci_dumpregs(host);
3563 }
3564
3565 return result;
3566 }
3567
sdhci_thread_irq(int irq,void * dev_id)3568 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3569 {
3570 struct sdhci_host *host = dev_id;
3571 struct mmc_command *cmd;
3572 unsigned long flags;
3573 u32 isr;
3574
3575 while (!sdhci_request_done(host))
3576 ;
3577
3578 spin_lock_irqsave(&host->lock, flags);
3579
3580 isr = host->thread_isr;
3581 host->thread_isr = 0;
3582
3583 cmd = host->deferred_cmd;
3584 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3585 sdhci_finish_mrq(host, cmd->mrq);
3586
3587 spin_unlock_irqrestore(&host->lock, flags);
3588
3589 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3590 struct mmc_host *mmc = host->mmc;
3591
3592 mmc->ops->card_event(mmc);
3593 mmc_detect_change(mmc, msecs_to_jiffies(200));
3594 }
3595
3596 return IRQ_HANDLED;
3597 }
3598
3599 /*****************************************************************************\
3600 * *
3601 * Suspend/resume *
3602 * *
3603 \*****************************************************************************/
3604
3605 #ifdef CONFIG_PM
3606
sdhci_cd_irq_can_wakeup(struct sdhci_host * host)3607 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3608 {
3609 return mmc_card_is_removable(host->mmc) &&
3610 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3611 !mmc_can_gpio_cd(host->mmc);
3612 }
3613
3614 /*
3615 * To enable wakeup events, the corresponding events have to be enabled in
3616 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3617 * Table' in the SD Host Controller Standard Specification.
3618 * It is useless to restore SDHCI_INT_ENABLE state in
3619 * sdhci_disable_irq_wakeups() since it will be set by
3620 * sdhci_enable_card_detection() or sdhci_init().
3621 */
sdhci_enable_irq_wakeups(struct sdhci_host * host)3622 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3623 {
3624 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3625 SDHCI_WAKE_ON_INT;
3626 u32 irq_val = 0;
3627 u8 wake_val = 0;
3628 u8 val;
3629
3630 if (sdhci_cd_irq_can_wakeup(host)) {
3631 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3632 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3633 }
3634
3635 if (mmc_card_wake_sdio_irq(host->mmc)) {
3636 wake_val |= SDHCI_WAKE_ON_INT;
3637 irq_val |= SDHCI_INT_CARD_INT;
3638 }
3639
3640 if (!irq_val)
3641 return false;
3642
3643 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3644 val &= ~mask;
3645 val |= wake_val;
3646 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3647
3648 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3649
3650 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3651
3652 return host->irq_wake_enabled;
3653 }
3654
sdhci_disable_irq_wakeups(struct sdhci_host * host)3655 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3656 {
3657 u8 val;
3658 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3659 | SDHCI_WAKE_ON_INT;
3660
3661 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3662 val &= ~mask;
3663 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3664
3665 disable_irq_wake(host->irq);
3666
3667 host->irq_wake_enabled = false;
3668 }
3669
sdhci_suspend_host(struct sdhci_host * host)3670 int sdhci_suspend_host(struct sdhci_host *host)
3671 {
3672 sdhci_disable_card_detection(host);
3673
3674 mmc_retune_timer_stop(host->mmc);
3675
3676 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3677 !sdhci_enable_irq_wakeups(host)) {
3678 host->ier = 0;
3679 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3680 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3681 free_irq(host->irq, host);
3682 }
3683
3684 return 0;
3685 }
3686
3687 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3688
sdhci_resume_host(struct sdhci_host * host)3689 int sdhci_resume_host(struct sdhci_host *host)
3690 {
3691 struct mmc_host *mmc = host->mmc;
3692 int ret = 0;
3693
3694 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3695 if (host->ops->enable_dma)
3696 host->ops->enable_dma(host);
3697 }
3698
3699 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3700 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3701 /* Card keeps power but host controller does not */
3702 sdhci_init(host, 0);
3703 host->pwr = 0;
3704 host->clock = 0;
3705 mmc->ops->set_ios(mmc, &mmc->ios);
3706 } else {
3707 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3708 }
3709
3710 if (host->irq_wake_enabled) {
3711 sdhci_disable_irq_wakeups(host);
3712 } else {
3713 ret = request_threaded_irq(host->irq, sdhci_irq,
3714 sdhci_thread_irq, IRQF_SHARED,
3715 mmc_hostname(host->mmc), host);
3716 if (ret)
3717 return ret;
3718 }
3719
3720 sdhci_enable_card_detection(host);
3721
3722 return ret;
3723 }
3724
3725 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3726
sdhci_runtime_suspend_host(struct sdhci_host * host)3727 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3728 {
3729 unsigned long flags;
3730
3731 mmc_retune_timer_stop(host->mmc);
3732
3733 spin_lock_irqsave(&host->lock, flags);
3734 host->ier &= SDHCI_INT_CARD_INT;
3735 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3736 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3737 spin_unlock_irqrestore(&host->lock, flags);
3738
3739 synchronize_hardirq(host->irq);
3740
3741 spin_lock_irqsave(&host->lock, flags);
3742 host->runtime_suspended = true;
3743 spin_unlock_irqrestore(&host->lock, flags);
3744
3745 return 0;
3746 }
3747 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3748
sdhci_runtime_resume_host(struct sdhci_host * host,int soft_reset)3749 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3750 {
3751 struct mmc_host *mmc = host->mmc;
3752 unsigned long flags;
3753 int host_flags = host->flags;
3754
3755 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3756 if (host->ops->enable_dma)
3757 host->ops->enable_dma(host);
3758 }
3759
3760 sdhci_init(host, soft_reset);
3761
3762 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3763 mmc->ios.power_mode != MMC_POWER_OFF) {
3764 /* Force clock and power re-program */
3765 host->pwr = 0;
3766 host->clock = 0;
3767 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3768 mmc->ops->set_ios(mmc, &mmc->ios);
3769
3770 if ((host_flags & SDHCI_PV_ENABLED) &&
3771 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3772 spin_lock_irqsave(&host->lock, flags);
3773 sdhci_enable_preset_value(host, true);
3774 spin_unlock_irqrestore(&host->lock, flags);
3775 }
3776
3777 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3778 mmc->ops->hs400_enhanced_strobe)
3779 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3780 }
3781
3782 spin_lock_irqsave(&host->lock, flags);
3783
3784 host->runtime_suspended = false;
3785
3786 /* Enable SDIO IRQ */
3787 if (sdio_irq_claimed(mmc))
3788 sdhci_enable_sdio_irq_nolock(host, true);
3789
3790 /* Enable Card Detection */
3791 sdhci_enable_card_detection(host);
3792
3793 spin_unlock_irqrestore(&host->lock, flags);
3794
3795 return 0;
3796 }
3797 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3798
3799 #endif /* CONFIG_PM */
3800
3801 /*****************************************************************************\
3802 * *
3803 * Command Queue Engine (CQE) helpers *
3804 * *
3805 \*****************************************************************************/
3806
sdhci_cqe_enable(struct mmc_host * mmc)3807 void sdhci_cqe_enable(struct mmc_host *mmc)
3808 {
3809 struct sdhci_host *host = mmc_priv(mmc);
3810 unsigned long flags;
3811 u8 ctrl;
3812
3813 spin_lock_irqsave(&host->lock, flags);
3814
3815 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3816 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3817 /*
3818 * Host from V4.10 supports ADMA3 DMA type.
3819 * ADMA3 performs integrated descriptor which is more suitable
3820 * for cmd queuing to fetch both command and transfer descriptors.
3821 */
3822 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3823 ctrl |= SDHCI_CTRL_ADMA3;
3824 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3825 ctrl |= SDHCI_CTRL_ADMA64;
3826 else
3827 ctrl |= SDHCI_CTRL_ADMA32;
3828 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3829
3830 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3831 SDHCI_BLOCK_SIZE);
3832
3833 /* Set maximum timeout */
3834 sdhci_set_timeout(host, NULL);
3835
3836 host->ier = host->cqe_ier;
3837
3838 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3839 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3840
3841 host->cqe_on = true;
3842
3843 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3844 mmc_hostname(mmc), host->ier,
3845 sdhci_readl(host, SDHCI_INT_STATUS));
3846
3847 spin_unlock_irqrestore(&host->lock, flags);
3848 }
3849 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3850
sdhci_cqe_disable(struct mmc_host * mmc,bool recovery)3851 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3852 {
3853 struct sdhci_host *host = mmc_priv(mmc);
3854 unsigned long flags;
3855
3856 spin_lock_irqsave(&host->lock, flags);
3857
3858 sdhci_set_default_irqs(host);
3859
3860 host->cqe_on = false;
3861
3862 if (recovery) {
3863 sdhci_do_reset(host, SDHCI_RESET_CMD);
3864 sdhci_do_reset(host, SDHCI_RESET_DATA);
3865 }
3866
3867 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3868 mmc_hostname(mmc), host->ier,
3869 sdhci_readl(host, SDHCI_INT_STATUS));
3870
3871 spin_unlock_irqrestore(&host->lock, flags);
3872 }
3873 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3874
sdhci_cqe_irq(struct sdhci_host * host,u32 intmask,int * cmd_error,int * data_error)3875 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3876 int *data_error)
3877 {
3878 u32 mask;
3879
3880 if (!host->cqe_on)
3881 return false;
3882
3883 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3884 *cmd_error = -EILSEQ;
3885 else if (intmask & SDHCI_INT_TIMEOUT)
3886 *cmd_error = -ETIMEDOUT;
3887 else
3888 *cmd_error = 0;
3889
3890 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3891 *data_error = -EILSEQ;
3892 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3893 *data_error = -ETIMEDOUT;
3894 else if (intmask & SDHCI_INT_ADMA_ERROR)
3895 *data_error = -EIO;
3896 else
3897 *data_error = 0;
3898
3899 /* Clear selected interrupts. */
3900 mask = intmask & host->cqe_ier;
3901 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3902
3903 if (intmask & SDHCI_INT_BUS_POWER)
3904 pr_err("%s: Card is consuming too much power!\n",
3905 mmc_hostname(host->mmc));
3906
3907 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3908 if (intmask) {
3909 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3910 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3911 mmc_hostname(host->mmc), intmask);
3912 sdhci_dumpregs(host);
3913 }
3914
3915 return true;
3916 }
3917 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3918
3919 /*****************************************************************************\
3920 * *
3921 * Device allocation/registration *
3922 * *
3923 \*****************************************************************************/
3924
sdhci_alloc_host(struct device * dev,size_t priv_size)3925 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3926 size_t priv_size)
3927 {
3928 struct mmc_host *mmc;
3929 struct sdhci_host *host;
3930
3931 WARN_ON(dev == NULL);
3932
3933 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3934 if (!mmc)
3935 return ERR_PTR(-ENOMEM);
3936
3937 host = mmc_priv(mmc);
3938 host->mmc = mmc;
3939 host->mmc_host_ops = sdhci_ops;
3940 mmc->ops = &host->mmc_host_ops;
3941
3942 host->flags = SDHCI_SIGNALING_330;
3943
3944 host->cqe_ier = SDHCI_CQE_INT_MASK;
3945 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3946
3947 host->tuning_delay = -1;
3948 host->tuning_loop_count = MAX_TUNING_LOOP;
3949
3950 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3951
3952 /*
3953 * The DMA table descriptor count is calculated as the maximum
3954 * number of segments times 2, to allow for an alignment
3955 * descriptor for each segment, plus 1 for a nop end descriptor.
3956 */
3957 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3958
3959 return host;
3960 }
3961
3962 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3963
sdhci_set_dma_mask(struct sdhci_host * host)3964 static int sdhci_set_dma_mask(struct sdhci_host *host)
3965 {
3966 struct mmc_host *mmc = host->mmc;
3967 struct device *dev = mmc_dev(mmc);
3968 int ret = -EINVAL;
3969
3970 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3971 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3972
3973 /* Try 64-bit mask if hardware is capable of it */
3974 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3975 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3976 if (ret) {
3977 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3978 mmc_hostname(mmc));
3979 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3980 }
3981 }
3982
3983 /* 32-bit mask as default & fallback */
3984 if (ret) {
3985 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3986 if (ret)
3987 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3988 mmc_hostname(mmc));
3989 }
3990
3991 return ret;
3992 }
3993
__sdhci_read_caps(struct sdhci_host * host,const u16 * ver,const u32 * caps,const u32 * caps1)3994 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3995 const u32 *caps, const u32 *caps1)
3996 {
3997 u16 v;
3998 u64 dt_caps_mask = 0;
3999 u64 dt_caps = 0;
4000
4001 if (host->read_caps)
4002 return;
4003
4004 host->read_caps = true;
4005
4006 if (debug_quirks)
4007 host->quirks = debug_quirks;
4008
4009 if (debug_quirks2)
4010 host->quirks2 = debug_quirks2;
4011
4012 sdhci_do_reset(host, SDHCI_RESET_ALL);
4013
4014 if (host->v4_mode)
4015 sdhci_do_enable_v4_mode(host);
4016
4017 device_property_read_u64_array(mmc_dev(host->mmc),
4018 "sdhci-caps-mask", &dt_caps_mask, 1);
4019 device_property_read_u64_array(mmc_dev(host->mmc),
4020 "sdhci-caps", &dt_caps, 1);
4021
4022 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4023 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4024
4025 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
4026 return;
4027
4028 if (caps) {
4029 host->caps = *caps;
4030 } else {
4031 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4032 host->caps &= ~lower_32_bits(dt_caps_mask);
4033 host->caps |= lower_32_bits(dt_caps);
4034 }
4035
4036 if (host->version < SDHCI_SPEC_300)
4037 return;
4038
4039 if (caps1) {
4040 host->caps1 = *caps1;
4041 } else {
4042 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4043 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4044 host->caps1 |= upper_32_bits(dt_caps);
4045 }
4046 }
4047 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4048
sdhci_allocate_bounce_buffer(struct sdhci_host * host)4049 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4050 {
4051 struct mmc_host *mmc = host->mmc;
4052 unsigned int max_blocks;
4053 unsigned int bounce_size;
4054 int ret;
4055
4056 /*
4057 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4058 * has diminishing returns, this is probably because SD/MMC
4059 * cards are usually optimized to handle this size of requests.
4060 */
4061 bounce_size = SZ_64K;
4062 /*
4063 * Adjust downwards to maximum request size if this is less
4064 * than our segment size, else hammer down the maximum
4065 * request size to the maximum buffer size.
4066 */
4067 if (mmc->max_req_size < bounce_size)
4068 bounce_size = mmc->max_req_size;
4069 max_blocks = bounce_size / 512;
4070
4071 /*
4072 * When we just support one segment, we can get significant
4073 * speedups by the help of a bounce buffer to group scattered
4074 * reads/writes together.
4075 */
4076 host->bounce_buffer = devm_kmalloc(mmc->parent,
4077 bounce_size,
4078 GFP_KERNEL);
4079 if (!host->bounce_buffer) {
4080 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4081 mmc_hostname(mmc),
4082 bounce_size);
4083 /*
4084 * Exiting with zero here makes sure we proceed with
4085 * mmc->max_segs == 1.
4086 */
4087 return;
4088 }
4089
4090 host->bounce_addr = dma_map_single(mmc->parent,
4091 host->bounce_buffer,
4092 bounce_size,
4093 DMA_BIDIRECTIONAL);
4094 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
4095 if (ret)
4096 /* Again fall back to max_segs == 1 */
4097 return;
4098 host->bounce_buffer_size = bounce_size;
4099
4100 /* Lie about this since we're bouncing */
4101 mmc->max_segs = max_blocks;
4102 mmc->max_seg_size = bounce_size;
4103 mmc->max_req_size = bounce_size;
4104
4105 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4106 mmc_hostname(mmc), max_blocks, bounce_size);
4107 }
4108
sdhci_can_64bit_dma(struct sdhci_host * host)4109 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4110 {
4111 /*
4112 * According to SD Host Controller spec v4.10, bit[27] added from
4113 * version 4.10 in Capabilities Register is used as 64-bit System
4114 * Address support for V4 mode.
4115 */
4116 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4117 return host->caps & SDHCI_CAN_64BIT_V4;
4118
4119 return host->caps & SDHCI_CAN_64BIT;
4120 }
4121
sdhci_setup_host(struct sdhci_host * host)4122 int sdhci_setup_host(struct sdhci_host *host)
4123 {
4124 struct mmc_host *mmc;
4125 u32 max_current_caps;
4126 unsigned int ocr_avail;
4127 unsigned int override_timeout_clk;
4128 u32 max_clk;
4129 int ret = 0;
4130 bool enable_vqmmc = false;
4131
4132 WARN_ON(host == NULL);
4133 if (host == NULL)
4134 return -EINVAL;
4135
4136 mmc = host->mmc;
4137
4138 /*
4139 * If there are external regulators, get them. Note this must be done
4140 * early before resetting the host and reading the capabilities so that
4141 * the host can take the appropriate action if regulators are not
4142 * available.
4143 */
4144 if (!mmc->supply.vqmmc) {
4145 ret = mmc_regulator_get_supply(mmc);
4146 if (ret)
4147 return ret;
4148 enable_vqmmc = true;
4149 }
4150
4151 DBG("Version: 0x%08x | Present: 0x%08x\n",
4152 sdhci_readw(host, SDHCI_HOST_VERSION),
4153 sdhci_readl(host, SDHCI_PRESENT_STATE));
4154 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4155 sdhci_readl(host, SDHCI_CAPABILITIES),
4156 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4157
4158 sdhci_read_caps(host);
4159
4160 override_timeout_clk = host->timeout_clk;
4161
4162 if (host->version > SDHCI_SPEC_420) {
4163 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4164 mmc_hostname(mmc), host->version);
4165 }
4166
4167 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4168 host->flags |= SDHCI_USE_SDMA;
4169 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4170 DBG("Controller doesn't have SDMA capability\n");
4171 else
4172 host->flags |= SDHCI_USE_SDMA;
4173
4174 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4175 (host->flags & SDHCI_USE_SDMA)) {
4176 DBG("Disabling DMA as it is marked broken\n");
4177 host->flags &= ~SDHCI_USE_SDMA;
4178 }
4179
4180 if ((host->version >= SDHCI_SPEC_200) &&
4181 (host->caps & SDHCI_CAN_DO_ADMA2))
4182 host->flags |= SDHCI_USE_ADMA;
4183
4184 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4185 (host->flags & SDHCI_USE_ADMA)) {
4186 DBG("Disabling ADMA as it is marked broken\n");
4187 host->flags &= ~SDHCI_USE_ADMA;
4188 }
4189
4190 if (sdhci_can_64bit_dma(host))
4191 host->flags |= SDHCI_USE_64_BIT_DMA;
4192
4193 if (host->use_external_dma) {
4194 ret = sdhci_external_dma_init(host);
4195 if (ret == -EPROBE_DEFER)
4196 goto unreg;
4197 /*
4198 * Fall back to use the DMA/PIO integrated in standard SDHCI
4199 * instead of external DMA devices.
4200 */
4201 else if (ret)
4202 sdhci_switch_external_dma(host, false);
4203 /* Disable internal DMA sources */
4204 else
4205 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4206 }
4207
4208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4209 if (host->ops->set_dma_mask)
4210 ret = host->ops->set_dma_mask(host);
4211 else
4212 ret = sdhci_set_dma_mask(host);
4213
4214 if (!ret && host->ops->enable_dma)
4215 ret = host->ops->enable_dma(host);
4216
4217 if (ret) {
4218 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4219 mmc_hostname(mmc));
4220 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4221
4222 ret = 0;
4223 }
4224 }
4225
4226 /* SDMA does not support 64-bit DMA if v4 mode not set */
4227 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4228 host->flags &= ~SDHCI_USE_SDMA;
4229
4230 if (host->flags & SDHCI_USE_ADMA) {
4231 dma_addr_t dma;
4232 void *buf;
4233
4234 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4235 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4236 else if (!host->alloc_desc_sz)
4237 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4238
4239 host->desc_sz = host->alloc_desc_sz;
4240 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4241
4242 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4243 /*
4244 * Use zalloc to zero the reserved high 32-bits of 128-bit
4245 * descriptors so that they never need to be written.
4246 */
4247 buf = dma_alloc_coherent(mmc_dev(mmc),
4248 host->align_buffer_sz + host->adma_table_sz,
4249 &dma, GFP_KERNEL);
4250 if (!buf) {
4251 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4252 mmc_hostname(mmc));
4253 host->flags &= ~SDHCI_USE_ADMA;
4254 } else if ((dma + host->align_buffer_sz) &
4255 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4256 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4257 mmc_hostname(mmc));
4258 host->flags &= ~SDHCI_USE_ADMA;
4259 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4260 host->adma_table_sz, buf, dma);
4261 } else {
4262 host->align_buffer = buf;
4263 host->align_addr = dma;
4264
4265 host->adma_table = buf + host->align_buffer_sz;
4266 host->adma_addr = dma + host->align_buffer_sz;
4267 }
4268 }
4269
4270 /*
4271 * If we use DMA, then it's up to the caller to set the DMA
4272 * mask, but PIO does not need the hw shim so we set a new
4273 * mask here in that case.
4274 */
4275 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4276 host->dma_mask = DMA_BIT_MASK(64);
4277 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4278 }
4279
4280 if (host->version >= SDHCI_SPEC_300)
4281 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4282 else
4283 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4284
4285 host->max_clk *= 1000000;
4286 if (host->max_clk == 0 || host->quirks &
4287 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4288 if (!host->ops->get_max_clock) {
4289 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4290 mmc_hostname(mmc));
4291 ret = -ENODEV;
4292 goto undma;
4293 }
4294 host->max_clk = host->ops->get_max_clock(host);
4295 }
4296
4297 /*
4298 * In case of Host Controller v3.00, find out whether clock
4299 * multiplier is supported.
4300 */
4301 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4302
4303 /*
4304 * In case the value in Clock Multiplier is 0, then programmable
4305 * clock mode is not supported, otherwise the actual clock
4306 * multiplier is one more than the value of Clock Multiplier
4307 * in the Capabilities Register.
4308 */
4309 if (host->clk_mul)
4310 host->clk_mul += 1;
4311
4312 /*
4313 * Set host parameters.
4314 */
4315 max_clk = host->max_clk;
4316
4317 if (host->ops->get_min_clock)
4318 mmc->f_min = host->ops->get_min_clock(host);
4319 else if (host->version >= SDHCI_SPEC_300) {
4320 if (host->clk_mul)
4321 max_clk = host->max_clk * host->clk_mul;
4322 /*
4323 * Divided Clock Mode minimum clock rate is always less than
4324 * Programmable Clock Mode minimum clock rate.
4325 */
4326 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4327 } else
4328 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4329
4330 if (!mmc->f_max || mmc->f_max > max_clk)
4331 mmc->f_max = max_clk;
4332
4333 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4334 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4335
4336 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4337 host->timeout_clk *= 1000;
4338
4339 if (host->timeout_clk == 0) {
4340 if (!host->ops->get_timeout_clock) {
4341 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4342 mmc_hostname(mmc));
4343 ret = -ENODEV;
4344 goto undma;
4345 }
4346
4347 host->timeout_clk =
4348 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4349 1000);
4350 }
4351
4352 if (override_timeout_clk)
4353 host->timeout_clk = override_timeout_clk;
4354
4355 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4356 host->ops->get_max_timeout_count(host) : 1 << 27;
4357 mmc->max_busy_timeout /= host->timeout_clk;
4358 }
4359
4360 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4361 !host->ops->get_max_timeout_count)
4362 mmc->max_busy_timeout = 0;
4363
4364 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
4365 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4366
4367 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4368 host->flags |= SDHCI_AUTO_CMD12;
4369
4370 /*
4371 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4372 * For v4 mode, SDMA may use Auto-CMD23 as well.
4373 */
4374 if ((host->version >= SDHCI_SPEC_300) &&
4375 ((host->flags & SDHCI_USE_ADMA) ||
4376 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4377 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4378 host->flags |= SDHCI_AUTO_CMD23;
4379 DBG("Auto-CMD23 available\n");
4380 } else {
4381 DBG("Auto-CMD23 unavailable\n");
4382 }
4383
4384 /*
4385 * A controller may support 8-bit width, but the board itself
4386 * might not have the pins brought out. Boards that support
4387 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4388 * their platform code before calling sdhci_add_host(), and we
4389 * won't assume 8-bit width for hosts without that CAP.
4390 */
4391 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4392 mmc->caps |= MMC_CAP_4_BIT_DATA;
4393
4394 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4395 mmc->caps &= ~MMC_CAP_CMD23;
4396
4397 if (host->caps & SDHCI_CAN_DO_HISPD)
4398 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4399
4400 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4401 mmc_card_is_removable(mmc) &&
4402 mmc_gpio_get_cd(host->mmc) < 0)
4403 mmc->caps |= MMC_CAP_NEEDS_POLL;
4404
4405 if (!IS_ERR(mmc->supply.vqmmc)) {
4406 if (enable_vqmmc) {
4407 ret = regulator_enable(mmc->supply.vqmmc);
4408 host->sdhci_core_to_disable_vqmmc = !ret;
4409 }
4410
4411 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4412 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4413 1950000))
4414 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4415 SDHCI_SUPPORT_SDR50 |
4416 SDHCI_SUPPORT_DDR50);
4417
4418 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4419 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4420 3600000))
4421 host->flags &= ~SDHCI_SIGNALING_330;
4422
4423 if (ret) {
4424 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4425 mmc_hostname(mmc), ret);
4426 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4427 }
4428
4429 }
4430
4431 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4432 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4433 SDHCI_SUPPORT_DDR50);
4434 /*
4435 * The SDHCI controller in a SoC might support HS200/HS400
4436 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4437 * but if the board is modeled such that the IO lines are not
4438 * connected to 1.8v then HS200/HS400 cannot be supported.
4439 * Disable HS200/HS400 if the board does not have 1.8v connected
4440 * to the IO lines. (Applicable for other modes in 1.8v)
4441 */
4442 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4443 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4444 }
4445
4446 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4447 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4448 SDHCI_SUPPORT_DDR50))
4449 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4450
4451 /* SDR104 supports also implies SDR50 support */
4452 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4453 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4454 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4455 * field can be promoted to support HS200.
4456 */
4457 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4458 mmc->caps2 |= MMC_CAP2_HS200;
4459 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4460 mmc->caps |= MMC_CAP_UHS_SDR50;
4461 }
4462
4463 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4464 (host->caps1 & SDHCI_SUPPORT_HS400))
4465 mmc->caps2 |= MMC_CAP2_HS400;
4466
4467 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4468 (IS_ERR(mmc->supply.vqmmc) ||
4469 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4470 1300000)))
4471 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4472
4473 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4474 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4475 mmc->caps |= MMC_CAP_UHS_DDR50;
4476
4477 /* Does the host need tuning for SDR50? */
4478 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4479 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4480
4481 /* Driver Type(s) (A, C, D) supported by the host */
4482 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4483 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4484 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4485 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4486 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4487 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4488
4489 /* Initial value for re-tuning timer count */
4490 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4491 host->caps1);
4492
4493 /*
4494 * In case Re-tuning Timer is not disabled, the actual value of
4495 * re-tuning timer will be 2 ^ (n - 1).
4496 */
4497 if (host->tuning_count)
4498 host->tuning_count = 1 << (host->tuning_count - 1);
4499
4500 /* Re-tuning mode supported by the Host Controller */
4501 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4502
4503 ocr_avail = 0;
4504
4505 /*
4506 * According to SD Host Controller spec v3.00, if the Host System
4507 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4508 * the value is meaningful only if Voltage Support in the Capabilities
4509 * register is set. The actual current value is 4 times the register
4510 * value.
4511 */
4512 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4513 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4514 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4515 if (curr > 0) {
4516
4517 /* convert to SDHCI_MAX_CURRENT format */
4518 curr = curr/1000; /* convert to mA */
4519 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4520
4521 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4522 max_current_caps =
4523 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4524 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4525 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
4526 }
4527 }
4528
4529 if (host->caps & SDHCI_CAN_VDD_330) {
4530 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4531
4532 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4533 max_current_caps) *
4534 SDHCI_MAX_CURRENT_MULTIPLIER;
4535 }
4536 if (host->caps & SDHCI_CAN_VDD_300) {
4537 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4538
4539 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4540 max_current_caps) *
4541 SDHCI_MAX_CURRENT_MULTIPLIER;
4542 }
4543 if (host->caps & SDHCI_CAN_VDD_180) {
4544 ocr_avail |= MMC_VDD_165_195;
4545
4546 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4547 max_current_caps) *
4548 SDHCI_MAX_CURRENT_MULTIPLIER;
4549 }
4550
4551 /* If OCR set by host, use it instead. */
4552 if (host->ocr_mask)
4553 ocr_avail = host->ocr_mask;
4554
4555 /* If OCR set by external regulators, give it highest prio. */
4556 if (mmc->ocr_avail)
4557 ocr_avail = mmc->ocr_avail;
4558
4559 mmc->ocr_avail = ocr_avail;
4560 mmc->ocr_avail_sdio = ocr_avail;
4561 if (host->ocr_avail_sdio)
4562 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4563 mmc->ocr_avail_sd = ocr_avail;
4564 if (host->ocr_avail_sd)
4565 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4566 else /* normal SD controllers don't support 1.8V */
4567 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4568 mmc->ocr_avail_mmc = ocr_avail;
4569 if (host->ocr_avail_mmc)
4570 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4571
4572 if (mmc->ocr_avail == 0) {
4573 pr_err("%s: Hardware doesn't report any support voltages.\n",
4574 mmc_hostname(mmc));
4575 ret = -ENODEV;
4576 goto unreg;
4577 }
4578
4579 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4580 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4581 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4582 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4583 host->flags |= SDHCI_SIGNALING_180;
4584
4585 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4586 host->flags |= SDHCI_SIGNALING_120;
4587
4588 spin_lock_init(&host->lock);
4589
4590 /*
4591 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4592 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4593 * is less anyway.
4594 */
4595 mmc->max_req_size = 524288;
4596
4597 /*
4598 * Maximum number of segments. Depends on if the hardware
4599 * can do scatter/gather or not.
4600 */
4601 if (host->flags & SDHCI_USE_ADMA) {
4602 mmc->max_segs = SDHCI_MAX_SEGS;
4603 } else if (host->flags & SDHCI_USE_SDMA) {
4604 mmc->max_segs = 1;
4605 if (swiotlb_max_segment()) {
4606 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4607 IO_TLB_SEGSIZE;
4608 mmc->max_req_size = min(mmc->max_req_size,
4609 max_req_size);
4610 }
4611 } else { /* PIO */
4612 mmc->max_segs = SDHCI_MAX_SEGS;
4613 }
4614
4615 /*
4616 * Maximum segment size. Could be one segment with the maximum number
4617 * of bytes. When doing hardware scatter/gather, each entry cannot
4618 * be larger than 64 KiB though.
4619 */
4620 if (host->flags & SDHCI_USE_ADMA) {
4621 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4622 mmc->max_seg_size = 65535;
4623 else
4624 mmc->max_seg_size = 65536;
4625 } else {
4626 mmc->max_seg_size = mmc->max_req_size;
4627 }
4628
4629 /*
4630 * Maximum block size. This varies from controller to controller and
4631 * is specified in the capabilities register.
4632 */
4633 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4634 mmc->max_blk_size = 2;
4635 } else {
4636 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4637 SDHCI_MAX_BLOCK_SHIFT;
4638 if (mmc->max_blk_size >= 3) {
4639 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4640 mmc_hostname(mmc));
4641 mmc->max_blk_size = 0;
4642 }
4643 }
4644
4645 mmc->max_blk_size = 512 << mmc->max_blk_size;
4646
4647 /*
4648 * Maximum block count.
4649 */
4650 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4651
4652 if (mmc->max_segs == 1)
4653 /* This may alter mmc->*_blk_* parameters */
4654 sdhci_allocate_bounce_buffer(host);
4655
4656 return 0;
4657
4658 unreg:
4659 if (host->sdhci_core_to_disable_vqmmc)
4660 regulator_disable(mmc->supply.vqmmc);
4661 undma:
4662 if (host->align_buffer)
4663 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4664 host->adma_table_sz, host->align_buffer,
4665 host->align_addr);
4666 host->adma_table = NULL;
4667 host->align_buffer = NULL;
4668
4669 return ret;
4670 }
4671 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4672
sdhci_cleanup_host(struct sdhci_host * host)4673 void sdhci_cleanup_host(struct sdhci_host *host)
4674 {
4675 struct mmc_host *mmc = host->mmc;
4676
4677 if (host->sdhci_core_to_disable_vqmmc)
4678 regulator_disable(mmc->supply.vqmmc);
4679
4680 if (host->align_buffer)
4681 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4682 host->adma_table_sz, host->align_buffer,
4683 host->align_addr);
4684
4685 if (host->use_external_dma)
4686 sdhci_external_dma_release(host);
4687
4688 host->adma_table = NULL;
4689 host->align_buffer = NULL;
4690 }
4691 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4692
__sdhci_add_host(struct sdhci_host * host)4693 int __sdhci_add_host(struct sdhci_host *host)
4694 {
4695 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4696 struct mmc_host *mmc = host->mmc;
4697 int ret;
4698
4699 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4700 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4701 mmc->caps2 &= ~MMC_CAP2_CQE;
4702 mmc->cqe_ops = NULL;
4703 }
4704
4705 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4706 if (!host->complete_wq)
4707 return -ENOMEM;
4708
4709 INIT_WORK(&host->complete_work, sdhci_complete_work);
4710
4711 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4712 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4713
4714 init_waitqueue_head(&host->buf_ready_int);
4715
4716 sdhci_init(host, 0);
4717
4718 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4719 IRQF_SHARED, mmc_hostname(mmc), host);
4720 if (ret) {
4721 pr_err("%s: Failed to request IRQ %d: %d\n",
4722 mmc_hostname(mmc), host->irq, ret);
4723 goto unwq;
4724 }
4725
4726 ret = sdhci_led_register(host);
4727 if (ret) {
4728 pr_err("%s: Failed to register LED device: %d\n",
4729 mmc_hostname(mmc), ret);
4730 goto unirq;
4731 }
4732
4733 ret = mmc_add_host(mmc);
4734 if (ret)
4735 goto unled;
4736
4737 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4738 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4739 host->use_external_dma ? "External DMA" :
4740 (host->flags & SDHCI_USE_ADMA) ?
4741 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4742 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4743
4744 sdhci_enable_card_detection(host);
4745
4746 return 0;
4747
4748 unled:
4749 sdhci_led_unregister(host);
4750 unirq:
4751 sdhci_do_reset(host, SDHCI_RESET_ALL);
4752 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4753 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4754 free_irq(host->irq, host);
4755 unwq:
4756 destroy_workqueue(host->complete_wq);
4757
4758 return ret;
4759 }
4760 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4761
sdhci_add_host(struct sdhci_host * host)4762 int sdhci_add_host(struct sdhci_host *host)
4763 {
4764 int ret;
4765
4766 ret = sdhci_setup_host(host);
4767 if (ret)
4768 return ret;
4769
4770 ret = __sdhci_add_host(host);
4771 if (ret)
4772 goto cleanup;
4773
4774 return 0;
4775
4776 cleanup:
4777 sdhci_cleanup_host(host);
4778
4779 return ret;
4780 }
4781 EXPORT_SYMBOL_GPL(sdhci_add_host);
4782
sdhci_remove_host(struct sdhci_host * host,int dead)4783 void sdhci_remove_host(struct sdhci_host *host, int dead)
4784 {
4785 struct mmc_host *mmc = host->mmc;
4786 unsigned long flags;
4787
4788 if (dead) {
4789 spin_lock_irqsave(&host->lock, flags);
4790
4791 host->flags |= SDHCI_DEVICE_DEAD;
4792
4793 if (sdhci_has_requests(host)) {
4794 pr_err("%s: Controller removed during "
4795 " transfer!\n", mmc_hostname(mmc));
4796 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4797 }
4798
4799 spin_unlock_irqrestore(&host->lock, flags);
4800 }
4801
4802 sdhci_disable_card_detection(host);
4803
4804 mmc_remove_host(mmc);
4805
4806 sdhci_led_unregister(host);
4807
4808 if (!dead)
4809 sdhci_do_reset(host, SDHCI_RESET_ALL);
4810
4811 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4812 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4813 free_irq(host->irq, host);
4814
4815 del_timer_sync(&host->timer);
4816 del_timer_sync(&host->data_timer);
4817
4818 destroy_workqueue(host->complete_wq);
4819
4820 if (host->sdhci_core_to_disable_vqmmc)
4821 regulator_disable(mmc->supply.vqmmc);
4822
4823 if (host->align_buffer)
4824 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4825 host->adma_table_sz, host->align_buffer,
4826 host->align_addr);
4827
4828 if (host->use_external_dma)
4829 sdhci_external_dma_release(host);
4830
4831 host->adma_table = NULL;
4832 host->align_buffer = NULL;
4833 }
4834
4835 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4836
sdhci_free_host(struct sdhci_host * host)4837 void sdhci_free_host(struct sdhci_host *host)
4838 {
4839 mmc_free_host(host->mmc);
4840 }
4841
4842 EXPORT_SYMBOL_GPL(sdhci_free_host);
4843
4844 /*****************************************************************************\
4845 * *
4846 * Driver init/exit *
4847 * *
4848 \*****************************************************************************/
4849
sdhci_drv_init(void)4850 static int __init sdhci_drv_init(void)
4851 {
4852 pr_info(DRIVER_NAME
4853 ": Secure Digital Host Controller Interface driver\n");
4854 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4855
4856 return 0;
4857 }
4858
sdhci_drv_exit(void)4859 static void __exit sdhci_drv_exit(void)
4860 {
4861 }
4862
4863 module_init(sdhci_drv_init);
4864 module_exit(sdhci_drv_exit);
4865
4866 module_param(debug_quirks, uint, 0444);
4867 module_param(debug_quirks2, uint, 0444);
4868
4869 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4870 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4871 MODULE_LICENSE("GPL");
4872
4873 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4874 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
4875