1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 *
6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */
10
11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H
13
14 enum {
15 TASK_REQ_UPIU_SIZE_DWORDS = 8,
16 TASK_RSP_UPIU_SIZE_DWORDS = 8,
17 ALIGNED_UPIU_SIZE = 512,
18 };
19
20 /* UFSHCI Registers */
21 enum {
22 REG_CONTROLLER_CAPABILITIES = 0x00,
23 REG_UFS_VERSION = 0x08,
24 REG_CONTROLLER_DEV_ID = 0x10,
25 REG_CONTROLLER_PROD_ID = 0x14,
26 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
27 REG_INTERRUPT_STATUS = 0x20,
28 REG_INTERRUPT_ENABLE = 0x24,
29 REG_CONTROLLER_STATUS = 0x30,
30 REG_CONTROLLER_ENABLE = 0x34,
31 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
32 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
33 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
34 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
35 REG_UIC_ERROR_CODE_DME = 0x48,
36 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
37 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
38 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
39 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
40 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
41 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
42 REG_UTP_TRANSFER_REQ_LIST_COMPL = 0x64,
43 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
44 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
45 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
46 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
47 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
48 REG_UIC_COMMAND = 0x90,
49 REG_UIC_COMMAND_ARG_1 = 0x94,
50 REG_UIC_COMMAND_ARG_2 = 0x98,
51 REG_UIC_COMMAND_ARG_3 = 0x9C,
52
53 UFSHCI_REG_SPACE_SIZE = 0xA0,
54
55 REG_UFS_CCAP = 0x100,
56 REG_UFS_CRYPTOCAP = 0x104,
57
58 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
59 };
60
61 /* Controller capability masks */
62 enum {
63 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
64 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
65 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
66 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
67 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
68 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
69 MASK_CRYPTO_SUPPORT = 0x10000000,
70 };
71
72 #define UFS_MASK(mask, offset) ((mask) << (offset))
73
74 /* UFS Version 08h */
75 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
76 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
77
78 /*
79 * Controller UFSHCI version
80 * - 2.x and newer use the following scheme:
81 * major << 8 + minor << 4
82 * - 1.x has been converted to match this in
83 * ufshcd_get_ufs_version()
84 */
ufshci_version(u32 major,u32 minor)85 static inline u32 ufshci_version(u32 major, u32 minor)
86 {
87 return (major << 8) + (minor << 4);
88 }
89
90 /*
91 * HCDDID - Host Controller Identification Descriptor
92 * - Device ID and Device Class 10h
93 */
94 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
95 #define DEVICE_ID UFS_MASK(0xFF, 24)
96
97 /*
98 * HCPMID - Host Controller Identification Descriptor
99 * - Product/Manufacturer ID 14h
100 */
101 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
102 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
103
104 /* AHIT - Auto-Hibernate Idle Timer */
105 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
106 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
107 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
108 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
109
110 /*
111 * IS - Interrupt Status - 20h
112 */
113 #define UTP_TRANSFER_REQ_COMPL 0x1
114 #define UIC_DME_END_PT_RESET 0x2
115 #define UIC_ERROR 0x4
116 #define UIC_TEST_MODE 0x8
117 #define UIC_POWER_MODE 0x10
118 #define UIC_HIBERNATE_EXIT 0x20
119 #define UIC_HIBERNATE_ENTER 0x40
120 #define UIC_LINK_LOST 0x80
121 #define UIC_LINK_STARTUP 0x100
122 #define UTP_TASK_REQ_COMPL 0x200
123 #define UIC_COMMAND_COMPL 0x400
124 #define DEVICE_FATAL_ERROR 0x800
125 #define CONTROLLER_FATAL_ERROR 0x10000
126 #define SYSTEM_BUS_FATAL_ERROR 0x20000
127 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
128
129 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
130 UIC_HIBERNATE_EXIT)
131
132 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
133 UIC_POWER_MODE)
134
135 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
136
137 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
138
139 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
140 CONTROLLER_FATAL_ERROR |\
141 SYSTEM_BUS_FATAL_ERROR |\
142 CRYPTO_ENGINE_FATAL_ERROR |\
143 UIC_LINK_LOST)
144
145 /* HCS - Host Controller Status 30h */
146 #define DEVICE_PRESENT 0x1
147 #define UTP_TRANSFER_REQ_LIST_READY 0x2
148 #define UTP_TASK_REQ_LIST_READY 0x4
149 #define UIC_COMMAND_READY 0x8
150 #define HOST_ERROR_INDICATOR 0x10
151 #define DEVICE_ERROR_INDICATOR 0x20
152 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
153
154 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
155 UTP_TASK_REQ_LIST_READY |\
156 UIC_COMMAND_READY)
157
158 enum {
159 PWR_OK = 0x0,
160 PWR_LOCAL = 0x01,
161 PWR_REMOTE = 0x02,
162 PWR_BUSY = 0x03,
163 PWR_ERROR_CAP = 0x04,
164 PWR_FATAL_ERROR = 0x05,
165 };
166
167 /* HCE - Host Controller Enable 34h */
168 #define CONTROLLER_ENABLE 0x1
169 #define CONTROLLER_DISABLE 0x0
170 #define CRYPTO_GENERAL_ENABLE 0x2
171
172 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
173 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
174 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
175 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
176 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
177
178 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
179 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
180 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
181 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
182 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
183 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
184 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
185 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
186 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
187 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
188
189 /* UECN - Host UIC Error Code Network Layer 40h */
190 #define UIC_NETWORK_LAYER_ERROR 0x80000000
191 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
192 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
193 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
194 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
195
196 /* UECT - Host UIC Error Code Transport Layer 44h */
197 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
198 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
199 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
200 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
201 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
202 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
203 #define UIC_TRANSPORT_BAD_TC 0x10
204 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
205 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
206
207 /* UECDME - Host UIC Error Code DME 48h */
208 #define UIC_DME_ERROR 0x80000000
209 #define UIC_DME_ERROR_CODE_MASK 0x1
210
211 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
212 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
213 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
214 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
215 #define INT_AGGR_STATUS_BIT 0x100000
216 #define INT_AGGR_PARAM_WRITE 0x1000000
217 #define INT_AGGR_ENABLE 0x80000000
218
219 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
220 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
221
222 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
223 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
224
225 /* UICCMD - UIC Command */
226 #define COMMAND_OPCODE_MASK 0xFF
227 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
228
229 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
230 #define RESET_LEVEL 0xFF
231
232 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
233 #define CONFIG_RESULT_CODE_MASK 0xFF
234 #define GENERIC_ERROR_CODE_MASK 0xFF
235
236 /* GenSelectorIndex calculation macros for M-PHY attributes */
237 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
238 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
239
240 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
241 ((sel) & 0xFFFF))
242 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
243 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
244 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
245
246 /* Link Status*/
247 enum link_status {
248 UFSHCD_LINK_IS_DOWN = 1,
249 UFSHCD_LINK_IS_UP = 2,
250 };
251
252 /* UIC Commands */
253 enum uic_cmd_dme {
254 UIC_CMD_DME_GET = 0x01,
255 UIC_CMD_DME_SET = 0x02,
256 UIC_CMD_DME_PEER_GET = 0x03,
257 UIC_CMD_DME_PEER_SET = 0x04,
258 UIC_CMD_DME_POWERON = 0x10,
259 UIC_CMD_DME_POWEROFF = 0x11,
260 UIC_CMD_DME_ENABLE = 0x12,
261 UIC_CMD_DME_RESET = 0x14,
262 UIC_CMD_DME_END_PT_RST = 0x15,
263 UIC_CMD_DME_LINK_STARTUP = 0x16,
264 UIC_CMD_DME_HIBER_ENTER = 0x17,
265 UIC_CMD_DME_HIBER_EXIT = 0x18,
266 UIC_CMD_DME_TEST_MODE = 0x1A,
267 };
268
269 /* UIC Config result code / Generic error code */
270 enum {
271 UIC_CMD_RESULT_SUCCESS = 0x00,
272 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
273 UIC_CMD_RESULT_FAILURE = 0x01,
274 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
275 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
276 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
277 UIC_CMD_RESULT_BAD_INDEX = 0x05,
278 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
279 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
280 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
281 UIC_CMD_RESULT_BUSY = 0x09,
282 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
283 };
284
285 #define MASK_UIC_COMMAND_RESULT 0xFF
286
287 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
288 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
289
290 /* Interrupt disable masks */
291 enum {
292 /* Interrupt disable mask for UFSHCI v1.0 */
293 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
294 INTERRUPT_MASK_RW_VER_10 = 0x30000,
295
296 /* Interrupt disable mask for UFSHCI v1.1 */
297 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
298
299 /* Interrupt disable mask for UFSHCI v2.1 */
300 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
301 };
302
303 /* CCAP - Crypto Capability 100h */
304 union ufs_crypto_capabilities {
305 __le32 reg_val;
306 struct {
307 u8 num_crypto_cap;
308 u8 config_count;
309 u8 reserved;
310 u8 config_array_ptr;
311 };
312 };
313
314 enum ufs_crypto_key_size {
315 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
316 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
317 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
318 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
319 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
320 };
321
322 enum ufs_crypto_alg {
323 UFS_CRYPTO_ALG_AES_XTS = 0x0,
324 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
325 UFS_CRYPTO_ALG_AES_ECB = 0x2,
326 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
327 };
328
329 /* x-CRYPTOCAP - Crypto Capability X */
330 union ufs_crypto_cap_entry {
331 __le32 reg_val;
332 struct {
333 u8 algorithm_id;
334 u8 sdus_mask; /* Supported data unit size mask */
335 u8 key_size;
336 u8 reserved;
337 };
338 };
339
340 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
341 #define UFS_CRYPTO_KEY_MAX_SIZE 64
342 /* x-CRYPTOCFG - Crypto Configuration X */
343 union ufs_crypto_cfg_entry {
344 __le32 reg_val[32];
345 struct {
346 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
347 u8 data_unit_size;
348 u8 crypto_cap_idx;
349 u8 reserved_1;
350 u8 config_enable;
351 u8 reserved_multi_host;
352 u8 reserved_2;
353 u8 vsb[2];
354 u8 reserved_3[56];
355 };
356 };
357
358 /*
359 * Request Descriptor Definitions
360 */
361
362 /* Transfer request command type */
363 enum {
364 UTP_CMD_TYPE_SCSI = 0x0,
365 UTP_CMD_TYPE_UFS = 0x1,
366 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
367 };
368
369 /* To accommodate UFS2.0 required Command type */
370 enum {
371 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
372 };
373
374 enum {
375 UTP_SCSI_COMMAND = 0x00000000,
376 UTP_NATIVE_UFS_COMMAND = 0x10000000,
377 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
378 UTP_REQ_DESC_INT_CMD = 0x01000000,
379 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
380 };
381
382 /* UTP Transfer Request Data Direction (DD) */
383 enum {
384 UTP_NO_DATA_TRANSFER = 0x00000000,
385 UTP_HOST_TO_DEVICE = 0x02000000,
386 UTP_DEVICE_TO_HOST = 0x04000000,
387 };
388
389 /* Overall command status values */
390 enum {
391 OCS_SUCCESS = 0x0,
392 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
393 OCS_INVALID_PRDT_ATTR = 0x2,
394 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
395 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
396 OCS_PEER_COMM_FAILURE = 0x5,
397 OCS_ABORTED = 0x6,
398 OCS_FATAL_ERROR = 0x7,
399 OCS_DEVICE_FATAL_ERROR = 0x8,
400 OCS_INVALID_CRYPTO_CONFIG = 0x9,
401 OCS_GENERAL_CRYPTO_ERROR = 0xA,
402 OCS_INVALID_COMMAND_STATUS = 0x0F,
403 MASK_OCS = 0x0F,
404 };
405
406 /* The maximum length of the data byte count field in the PRDT is 256KB */
407 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
408 /* The granularity of the data byte count field in the PRDT is 32-bit */
409 #define PRDT_DATA_BYTE_COUNT_PAD 4
410
411 /**
412 * struct ufshcd_sg_entry - UFSHCI PRD Entry
413 * @base_addr: Lower 32bit physical address DW-0
414 * @upper_addr: Upper 32bit physical address DW-1
415 * @reserved: Reserved for future use DW-2
416 * @size: size of physical segment DW-3
417 */
418 struct ufshcd_sg_entry {
419 __le32 base_addr;
420 __le32 upper_addr;
421 __le32 reserved;
422 __le32 size;
423 /*
424 * followed by variant-specific fields if
425 * hba->sg_entry_size != sizeof(struct ufshcd_sg_entry)
426 */
427 };
428
429 /**
430 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
431 * @command_upiu: Command UPIU Frame address
432 * @response_upiu: Response UPIU Frame address
433 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
434 * ufshcd_sg_entry's. Variant-specific fields may be present after each.
435 */
436 struct utp_transfer_cmd_desc {
437 u8 command_upiu[ALIGNED_UPIU_SIZE];
438 u8 response_upiu[ALIGNED_UPIU_SIZE];
439 u8 prd_table[];
440 };
441
442 #define sizeof_utp_transfer_cmd_desc(hba) \
443 (sizeof(struct utp_transfer_cmd_desc) + SG_ALL * (hba)->sg_entry_size)
444
445 /**
446 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
447 * @dword0: Descriptor Header DW0
448 * @dword1: Descriptor Header DW1
449 * @dword2: Descriptor Header DW2
450 * @dword3: Descriptor Header DW3
451 */
452 struct request_desc_header {
453 __le32 dword_0;
454 __le32 dword_1;
455 __le32 dword_2;
456 __le32 dword_3;
457 };
458
459 /**
460 * struct utp_transfer_req_desc - UTRD structure
461 * @header: UTRD header DW-0 to DW-3
462 * @command_desc_base_addr_lo: UCD base address low DW-4
463 * @command_desc_base_addr_hi: UCD base address high DW-5
464 * @response_upiu_length: response UPIU length DW-6
465 * @response_upiu_offset: response UPIU offset DW-6
466 * @prd_table_length: Physical region descriptor length DW-7
467 * @prd_table_offset: Physical region descriptor offset DW-7
468 */
469 struct utp_transfer_req_desc {
470
471 /* DW 0-3 */
472 struct request_desc_header header;
473
474 /* DW 4-5*/
475 __le32 command_desc_base_addr_lo;
476 __le32 command_desc_base_addr_hi;
477
478 /* DW 6 */
479 __le16 response_upiu_length;
480 __le16 response_upiu_offset;
481
482 /* DW 7 */
483 __le16 prd_table_length;
484 __le16 prd_table_offset;
485 };
486
487 /*
488 * UTMRD structure.
489 */
490 struct utp_task_req_desc {
491 /* DW 0-3 */
492 struct request_desc_header header;
493
494 /* DW 4-11 - Task request UPIU structure */
495 struct utp_upiu_header req_header;
496 __be32 input_param1;
497 __be32 input_param2;
498 __be32 input_param3;
499 __be32 __reserved1[2];
500
501 /* DW 12-19 - Task Management Response UPIU structure */
502 struct utp_upiu_header rsp_header;
503 __be32 output_param1;
504 __be32 output_param2;
505 __be32 __reserved2[3];
506 };
507
508 #endif /* End of Header */
509