67 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \  argument
68 	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
70 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \  argument
72 	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
75 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \  argument
76 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
78 #define imx_clk_pfd(name, parent_name, reg, idx) \  argument
79 	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
129 #define imx_clk_frac_pll(name, parent_name, base) \  argument
130 	to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
137 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
140 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \  argument
141 	to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
144 				const char *parent_name, void __iomem *base,
153 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
177 		const char *parent_name, void __iomem *base, u32 div_mask);
196 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
200 		const char *parent_name, unsigned long flags,
217 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
220 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
223 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
252 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,  in imx_clk_hw_pll14xx()  argument
256 	return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);  in imx_clk_hw_pll14xx()
532 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
600 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,