23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\  argument
29 		.name = "aud_"#_name,					\
37 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) {	\  argument
45 		.name = "aud_"#_name,					\
53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \  argument
61 		.name = "aud_"#_name,					\
69 #define AUD_PCLK_GATE(_name, _reg, _bit) {				\  argument
75 		.name = "aud_"#_name,					\
82 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\  argument
97 		.name = "aud_"#_name,					\
105 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,	\  argument
125 		.name = "aud_"#_name,					\
133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {	\  argument
142 		.name = "aud_"#_name,					\
150 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname,	\  argument
165 		.name = "aud_"#_name,					\
185 #define AUD_MST_MUX(_name, _reg, _flag)					\  argument
186 	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,			\
188 #define AUD_MST_DIV(_name, _reg, _flag)					\  argument
189 	AUD_DIV(_name##_div, _reg, 0, 16, _flag,			\
190 		aud_##_name##_sel, CLK_SET_RATE_PARENT)
191 #define AUD_MST_MCLK_GATE(_name, _reg)					\  argument
192 	AUD_GATE(_name, _reg, 31, aud_##_name##_div,			\
195 #define AUD_MST_MCLK_MUX(_name, _reg)					\  argument
196 	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
197 #define AUD_MST_MCLK_DIV(_name, _reg)					\  argument
198 	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
200 #define AUD_MST_SYS_MUX(_name, _reg)					\  argument
201 	AUD_MST_MUX(_name, _reg, 0)
202 #define AUD_MST_SYS_DIV(_name, _reg)					\  argument
203 	AUD_MST_DIV(_name, _reg, 0)
206 #define AUD_MST_SCLK_PRE_EN(_name, _reg)				\  argument
207 	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,			\
208 		 aud_mst_##_name##_mclk, 0)
209 #define AUD_MST_SCLK_DIV(_name, _reg)					\  argument
210 	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
211 		     aud_mst_##_name##_sclk_pre_en,			\
213 #define AUD_MST_SCLK_POST_EN(_name, _reg)				\  argument
214 	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
215 		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
216 #define AUD_MST_SCLK(_name, _reg)					\  argument
217 	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
218 		     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
220 #define AUD_MST_LRCLK_DIV(_name, _reg)					\  argument
221 	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
222 		     aud_mst_##_name##_sclk_post_en, 0)
223 #define AUD_MST_LRCLK(_name, _reg)					\  argument
224 	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
225 		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
267 #define AUD_TDM_SCLK_MUX(_name, _reg)					\  argument
268 	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,			\
270 #define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\  argument
271 	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
272 		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
273 #define AUD_TDM_SCLK_POST_EN(_name, _reg)				\  argument
274 	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
275 		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
276 #define AUD_TDM_SCLK(_name, _reg)					\  argument
277 	AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,			\
278 		  aud_tdm##_name##_sclk_post_en,			\
280 #define AUD_TDM_SCLK_WS(_name, _reg)					\  argument
281 	AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28,			\
282 		    aud_tdm##_name##_sclk_post_en,			\
285 #define AUD_TDM_LRLCK(_name, _reg)					\  argument
286 	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,			\
319 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\  argument
320 	AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,		\