Lines Matching refs:rcg
45 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) argument
46 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) argument
47 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) argument
48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) argument
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_is_enabled() local
69 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
78 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_get_parent() local
83 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_get_parent()
91 if (cfg == rcg->parent_map[i].cfg) in clk_rcg2_get_parent()
100 static int update_config(struct clk_rcg2 *rcg) in update_config() argument
104 struct clk_hw *hw = &rcg->clkr.hw; in update_config()
107 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in update_config()
114 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in update_config()
128 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_set_parent() local
130 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_rcg2_set_parent()
132 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), in clk_rcg2_set_parent()
137 return update_config(rcg); in clk_rcg2_set_parent()
162 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_recalc_rate() local
165 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_recalc_rate()
167 if (rcg->mnd_width) { in clk_rcg2_recalc_rate()
168 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_recalc_rate()
169 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in clk_rcg2_recalc_rate()
171 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); in clk_rcg2_recalc_rate()
179 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_recalc_rate()
192 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in _freq_tbl_determine_rate() local
209 index = qcom_find_src_index(hw, rcg->parent_map, f->src); in _freq_tbl_determine_rate()
246 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_determine_rate() local
248 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); in clk_rcg2_determine_rate()
254 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_determine_floor_rate() local
256 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); in clk_rcg2_determine_floor_rate()
259 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) in __clk_rcg2_configure() argument
262 struct clk_hw *hw = &rcg->clkr.hw; in __clk_rcg2_configure()
263 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); in __clk_rcg2_configure()
268 if (rcg->mnd_width && f->n) { in __clk_rcg2_configure()
269 mask = BIT(rcg->mnd_width) - 1; in __clk_rcg2_configure()
270 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure()
271 RCG_M_OFFSET(rcg), mask, f->m); in __clk_rcg2_configure()
275 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure()
276 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); in __clk_rcg2_configure()
289 ret = regmap_update_bits(rcg->clkr.regmap, in __clk_rcg2_configure()
290 RCG_D_OFFSET(rcg), mask, not2d_val); in __clk_rcg2_configure()
295 mask = BIT(rcg->hid_width) - 1; in __clk_rcg2_configure()
298 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in __clk_rcg2_configure()
299 if (rcg->mnd_width && f->n && (f->m != f->n)) in __clk_rcg2_configure()
301 return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), in __clk_rcg2_configure()
305 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) in clk_rcg2_configure() argument
309 ret = __clk_rcg2_configure(rcg, f); in clk_rcg2_configure()
313 return update_config(rcg); in clk_rcg2_configure()
319 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_set_rate() local
324 f = qcom_find_freq_floor(rcg->freq_tbl, rate); in __clk_rcg2_set_rate()
327 f = qcom_find_freq(rcg->freq_tbl, rate); in __clk_rcg2_set_rate()
336 return clk_rcg2_configure(rcg, f); in __clk_rcg2_set_rate()
415 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_edp_pixel_set_rate() local
416 struct freq_tbl f = *rcg->freq_tbl; in clk_edp_pixel_set_rate()
421 u32 mask = BIT(rcg->hid_width) - 1; in clk_edp_pixel_set_rate()
437 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_set_rate()
445 return clk_rcg2_configure(rcg, &f); in clk_edp_pixel_set_rate()
461 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_edp_pixel_determine_rate() local
462 const struct freq_tbl *f = rcg->freq_tbl; in clk_edp_pixel_determine_rate()
466 u32 mask = BIT(rcg->hid_width) - 1; in clk_edp_pixel_determine_rate()
468 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); in clk_edp_pixel_determine_rate()
487 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_edp_pixel_determine_rate()
515 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte_determine_rate() local
516 const struct freq_tbl *f = rcg->freq_tbl; in clk_byte_determine_rate()
517 int index = qcom_find_src_index(hw, rcg->parent_map, f->src); in clk_byte_determine_rate()
519 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte_determine_rate()
539 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte_set_rate() local
540 struct freq_tbl f = *rcg->freq_tbl; in clk_byte_set_rate()
542 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte_set_rate()
549 return clk_rcg2_configure(rcg, &f); in clk_byte_set_rate()
573 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte2_determine_rate() local
575 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte2_determine_rate()
596 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_byte2_set_rate() local
600 u32 mask = BIT(rcg->hid_width) - 1; in clk_byte2_set_rate()
608 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_byte2_set_rate()
613 if (cfg == rcg->parent_map[i].cfg) { in clk_byte2_set_rate()
614 f.src = rcg->parent_map[i].src; in clk_byte2_set_rate()
615 return clk_rcg2_configure(rcg, &f); in clk_byte2_set_rate()
675 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_pixel_set_rate() local
680 u32 mask = BIT(rcg->hid_width) - 1; in clk_pixel_set_rate()
684 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_pixel_set_rate()
689 if (cfg == rcg->parent_map[i].cfg) { in clk_pixel_set_rate()
690 f.src = rcg->parent_map[i].src; in clk_pixel_set_rate()
701 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_pixel_set_rate()
709 return clk_rcg2_configure(rcg, &f); in clk_pixel_set_rate()
783 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_gfx3d_set_rate_and_parent() local
788 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; in clk_gfx3d_set_rate_and_parent()
789 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); in clk_gfx3d_set_rate_and_parent()
793 return update_config(rcg); in clk_gfx3d_set_rate_and_parent()
820 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_set_force_enable() local
824 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in clk_rcg2_set_force_enable()
843 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_clear_force_enable() local
845 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, in clk_rcg2_clear_force_enable()
852 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_force_enable_clear() local
859 ret = clk_rcg2_configure(rcg, f); in clk_rcg2_shared_force_enable_clear()
869 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_set_rate() local
872 f = qcom_find_freq(rcg->freq_tbl, rate); in clk_rcg2_shared_set_rate()
881 return __clk_rcg2_configure(rcg, f); in clk_rcg2_shared_set_rate()
894 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_enable() local
905 ret = update_config(rcg); in clk_rcg2_shared_enable()
914 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_shared_disable() local
921 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_rcg2_shared_disable()
933 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, in clk_rcg2_shared_disable()
934 rcg->safe_src_index << CFG_SRC_SEL_SHIFT); in clk_rcg2_shared_disable()
936 update_config(rcg); in clk_rcg2_shared_disable()
941 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); in clk_rcg2_shared_disable()
960 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dfs_populate_freq() local
966 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); in clk_rcg2_dfs_populate_freq()
968 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dfs_populate_freq()
978 if (src == rcg->parent_map[i].cfg) { in clk_rcg2_dfs_populate_freq()
979 f->src = rcg->parent_map[i].src; in clk_rcg2_dfs_populate_freq()
980 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); in clk_rcg2_dfs_populate_freq()
988 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_dfs_populate_freq()
989 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l), in clk_rcg2_dfs_populate_freq()
994 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l), in clk_rcg2_dfs_populate_freq()
1005 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg) in clk_rcg2_dfs_populate_freq_table() argument
1014 rcg->freq_tbl = freq_tbl; in clk_rcg2_dfs_populate_freq_table()
1017 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i); in clk_rcg2_dfs_populate_freq_table()
1025 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dfs_determine_rate() local
1028 if (!rcg->freq_tbl) { in clk_rcg2_dfs_determine_rate()
1029 ret = clk_rcg2_dfs_populate_freq_table(rcg); in clk_rcg2_dfs_determine_rate()
1043 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dfs_recalc_rate() local
1046 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1047 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level); in clk_rcg2_dfs_recalc_rate()
1051 if (rcg->freq_tbl) in clk_rcg2_dfs_recalc_rate()
1052 return rcg->freq_tbl[level].freq; in clk_rcg2_dfs_recalc_rate()
1061 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level), in clk_rcg2_dfs_recalc_rate()
1064 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dfs_recalc_rate()
1072 mask = BIT(rcg->mnd_width) - 1; in clk_rcg2_dfs_recalc_rate()
1073 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1074 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m); in clk_rcg2_dfs_recalc_rate()
1077 regmap_read(rcg->clkr.regmap, in clk_rcg2_dfs_recalc_rate()
1078 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n); in clk_rcg2_dfs_recalc_rate()
1097 struct clk_rcg2 *rcg = data->rcg; in clk_rcg2_enable_dfs() local
1102 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); in clk_rcg2_enable_dfs()
1116 rcg->freq_tbl = NULL; in clk_rcg2_enable_dfs()
1139 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dp_set_rate() local
1141 u32 mask = BIT(rcg->hid_width) - 1; in clk_rcg2_dp_set_rate()
1147 GENMASK(rcg->mnd_width - 1, 0), in clk_rcg2_dp_set_rate()
1148 GENMASK(rcg->mnd_width - 1, 0), &den, &num); in clk_rcg2_dp_set_rate()
1153 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); in clk_rcg2_dp_set_rate()
1159 if (cfg == rcg->parent_map[i].cfg) { in clk_rcg2_dp_set_rate()
1160 f.src = rcg->parent_map[i].src; in clk_rcg2_dp_set_rate()
1177 return clk_rcg2_configure(rcg, &f); in clk_rcg2_dp_set_rate()
1189 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_dp_determine_rate() local
1195 GENMASK(rcg->mnd_width - 1, 0), in clk_rcg2_dp_determine_rate()
1196 GENMASK(rcg->mnd_width - 1, 0), &den, &num); in clk_rcg2_dp_determine_rate()