Lines Matching refs:PNAME

136 PNAME(mux_pll_p)		= { "xin24m"};
137 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
138 PNAME(mux_armclk_p)		= { "apll_core", "gpll_core" };
139 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
140 PNAME(mux_ddrstdby_p)		= { "clk_ddrphy1x", "clk_stdby_2wrap" };
141 PNAME(mux_4plls_p)		= { "gpll", "dummy_cpll", "usb480m", "npll" };
142 PNAME(mux_cpll_npll_p)		= { "cpll", "npll" };
143 PNAME(mux_npll_cpll_p)		= { "npll", "cpll" };
144 PNAME(mux_gpll_cpll_p)		= { "gpll", "dummy_cpll" };
145 PNAME(mux_gpll_npll_p)		= { "gpll", "npll" };
146 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m"};
147 PNAME(mux_gpll_cpll_npll_p)		= { "gpll", "dummy_cpll", "npll" };
148 PNAME(mux_gpll_cpll_npll_xin24m_p)	= { "gpll", "dummy_cpll", "npll", "xin24m" };
149 PNAME(mux_gpll_xin24m_npll_p)		= { "gpll", "xin24m", "npll"};
150 PNAME(mux_pdm_p)		= { "clk_pdm_src", "clk_pdm_frac" };
151 PNAME(mux_i2s0_tx_p)		= { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
152 PNAME(mux_i2s0_rx_p)		= { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
153 PNAME(mux_i2s1_p)		= { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
154 PNAME(mux_i2s2_p)		= { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
155 PNAME(mux_i2s0_tx_out_p)	= { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
156 PNAME(mux_i2s0_rx_out_p)	= { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
157 PNAME(mux_i2s1_out_p)		= { "clk_i2s1", "xin12m"};
158 PNAME(mux_i2s2_out_p)		= { "clk_i2s2", "xin12m"};
159 PNAME(mux_i2s0_tx_rx_p)		= { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
160 PNAME(mux_i2s0_rx_tx_p)		= { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
161 PNAME(mux_uart_src_p)		= { "gpll", "xin24m", "usb480m", "npll" };
162 PNAME(mux_uart1_p)		= { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
163 PNAME(mux_uart2_p)		= { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
164 PNAME(mux_uart3_p)		= { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
165 PNAME(mux_uart4_p)		= { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
166 PNAME(mux_uart5_p)		= { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
167 PNAME(mux_cif_out_p)		= { "xin24m", "dummy_cpll", "npll", "usb480m" };
168 PNAME(mux_dclk_vopb_p)		= { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
169 PNAME(mux_dclk_vopl_p)		= { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
170 PNAME(mux_nandc_p)		= { "clk_nandc_div", "clk_nandc_div50" };
171 PNAME(mux_sdio_p)		= { "clk_sdio_div", "clk_sdio_div50" };
172 PNAME(mux_emmc_p)		= { "clk_emmc_div", "clk_emmc_div50" };
173 PNAME(mux_sdmmc_p)		= { "clk_sdmmc_div", "clk_sdmmc_div50" };
174 PNAME(mux_gmac_p)		= { "clk_gmac_src", "gmac_clkin" };
175 PNAME(mux_gmac_rmii_sel_p)	= { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
176 PNAME(mux_rtc32k_pmu_p)		= { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
177 PNAME(mux_wifi_pmu_p)		= { "xin24m", "clk_wifi_pmu_src" };
178 PNAME(mux_uart0_pmu_p)		= { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
179 PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_ref24m_pmu" };
180 PNAME(mux_mipidsiphy_ref_p)	= { "xin24m", "clk_ref24m_pmu" };
181 PNAME(mux_gpu_p)		= { "clk_gpu_div", "clk_gpu_np5" };