Lines Matching refs:MUX
250 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
254 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
258 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
262 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
266 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
270 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
328 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
333 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
355 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
406 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
546 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
550 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
554 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
581 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
586 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
592 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
613 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
670 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
721 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,