29 #define CLK_EN1			(topcrm_base + 0x10)  macro
453 		zx_gate("nandflash_ahb_hclk", "main_hclk",	CLK_EN1, 0);  in zx296702_top_clocks_init()
455 		zx_gate("nandflash_wclk",     "nand_wclk_mux",	CLK_EN1, 1);  in zx296702_top_clocks_init()
457 		zx_gate("lsp0_apb_pclk",	"main_pclk",	CLK_EN1, 2);  in zx296702_top_clocks_init()
459 		zx_gate("lsp0_ahb_hclk",	"main_hclk",	CLK_EN1, 3);  in zx296702_top_clocks_init()
461 		zx_gate("lsp0_26M_wclk",   "lsp_26_wclk_mux",	CLK_EN1, 4);  in zx296702_top_clocks_init()
463 		zx_gate("lsp0_104M_wclk",	"pll_lsp_104M",	CLK_EN1, 5);  in zx296702_top_clocks_init()
465 		zx_gate("lsp0_16M384_wclk",	"clk_16M384",	CLK_EN1, 6);  in zx296702_top_clocks_init()
467 		zx_gate("lsp1_apb_pclk",	"main_pclk",	CLK_EN1, 7);  in zx296702_top_clocks_init()
471 		zx_gate("lsp1_26M_wclk",     "lsp_26_wclk_mux",	CLK_EN1, 31);  in zx296702_top_clocks_init()
473 		zx_gate("lsp1_104M_wclk",    "pll_lsp_104M",	CLK_EN1, 9);  in zx296702_top_clocks_init()
475 		zx_gate("lsp1_32K_clk",	"clk_32K768",		CLK_EN1, 10);  in zx296702_top_clocks_init()
477 		zx_gate("aon_hclk",		"main_hclk",	CLK_EN1, 11);  in zx296702_top_clocks_init()
479 		zx_gate("sys_ctrl_pclk",	"main_pclk",	CLK_EN1, 12);  in zx296702_top_clocks_init()
481 		zx_gate("dma_pclk",		"main_pclk",	CLK_EN1, 13);  in zx296702_top_clocks_init()
483 		zx_gate("dma_aclk",		"matrix_aclk",	CLK_EN1, 14);  in zx296702_top_clocks_init()
485 		zx_gate("sec_hclk",		"main_hclk",	CLK_EN1, 15);  in zx296702_top_clocks_init()
487 		zx_gate("aes_wclk",		"sec_wclk_div",	CLK_EN1, 16);  in zx296702_top_clocks_init()
489 		zx_gate("des_wclk",		"sec_wclk_div",	CLK_EN1, 17);  in zx296702_top_clocks_init()
491 		zx_gate("iram_aclk",		"matrix_aclk",	CLK_EN1, 18);  in zx296702_top_clocks_init()
493 		zx_gate("irom_aclk",		"matrix_aclk",	CLK_EN1, 19);  in zx296702_top_clocks_init()
495 		zx_gate("boot_ctrl_hclk",	"main_hclk",	CLK_EN1, 20);  in zx296702_top_clocks_init()
497 		zx_gate("efuse_clk_30",	"osc",			CLK_EN1, 21);  in zx296702_top_clocks_init()