Lines Matching refs:ndev
14 static void emu_enable_cores(struct nitrox_device *ndev) in emu_enable_cores() argument
30 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value); in emu_enable_cores()
31 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value); in emu_enable_cores()
39 void nitrox_config_emu_unit(struct nitrox_device *ndev) in nitrox_config_emu_unit() argument
47 emu_enable_cores(ndev); in nitrox_config_emu_unit()
58 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
60 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
64 static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring) in reset_pkt_input_ring() argument
73 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
75 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
80 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
88 pkt_in_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
89 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
93 void enable_pkt_input_ring(struct nitrox_device *ndev, int ring) in enable_pkt_input_ring() argument
101 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
104 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
108 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
119 void nitrox_config_pkt_input_rings(struct nitrox_device *ndev) in nitrox_config_pkt_input_rings() argument
123 for (i = 0; i < ndev->nr_queues; i++) { in nitrox_config_pkt_input_rings()
124 struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i]; in nitrox_config_pkt_input_rings()
129 reset_pkt_input_ring(ndev, i); in nitrox_config_pkt_input_rings()
137 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
142 pkt_in_rsize.s.rsize = ndev->qlen; in nitrox_config_pkt_input_rings()
143 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
147 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
153 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in nitrox_config_pkt_input_rings()
156 enable_pkt_input_ring(ndev, i); in nitrox_config_pkt_input_rings()
160 static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port) in reset_pkt_solicit_port() argument
169 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
171 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
177 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
185 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
186 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
190 void enable_pkt_solicit_port(struct nitrox_device *ndev, int port) in enable_pkt_solicit_port() argument
206 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
210 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_solicit_port()
217 static void config_pkt_solicit_port(struct nitrox_device *ndev, int port) in config_pkt_solicit_port() argument
222 reset_pkt_solicit_port(ndev, port); in config_pkt_solicit_port()
229 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_pkt_solicit_port()
232 enable_pkt_solicit_port(ndev, port); in config_pkt_solicit_port()
235 void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev) in nitrox_config_pkt_solicit_ports() argument
239 for (i = 0; i < ndev->nr_queues; i++) in nitrox_config_pkt_solicit_ports()
240 config_pkt_solicit_port(ndev, i); in nitrox_config_pkt_solicit_ports()
249 static void enable_nps_core_interrupts(struct nitrox_device *ndev) in enable_nps_core_interrupts() argument
260 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value); in enable_nps_core_interrupts()
263 void nitrox_config_nps_core_unit(struct nitrox_device *ndev) in nitrox_config_nps_core_unit() argument
268 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL); in nitrox_config_nps_core_unit()
274 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value); in nitrox_config_nps_core_unit()
277 enable_nps_core_interrupts(ndev); in nitrox_config_nps_core_unit()
286 static void enable_nps_pkt_interrupts(struct nitrox_device *ndev) in enable_nps_pkt_interrupts() argument
289 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
291 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
293 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
295 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL)); in enable_nps_pkt_interrupts()
298 void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev) in nitrox_config_nps_pkt_unit() argument
301 nitrox_config_pkt_input_rings(ndev); in nitrox_config_nps_pkt_unit()
302 nitrox_config_pkt_solicit_ports(ndev); in nitrox_config_nps_pkt_unit()
305 enable_nps_pkt_interrupts(ndev); in nitrox_config_nps_pkt_unit()
308 static void reset_aqm_ring(struct nitrox_device *ndev, int ring) in reset_aqm_ring() argument
320 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in reset_aqm_ring()
326 activity_stat.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
334 cmp_cnt.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
335 nitrox_write_csr(ndev, offset, cmp_cnt.value); in reset_aqm_ring()
339 void enable_aqm_ring(struct nitrox_device *ndev, int ring) in enable_aqm_ring() argument
347 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in enable_aqm_ring()
351 void nitrox_config_aqm_rings(struct nitrox_device *ndev) in nitrox_config_aqm_rings() argument
355 for (ring = 0; ring < ndev->nr_queues; ring++) { in nitrox_config_aqm_rings()
356 struct nitrox_cmdq *cmdq = ndev->aqmq[ring]; in nitrox_config_aqm_rings()
363 reset_aqm_ring(ndev, ring); in nitrox_config_aqm_rings()
369 nitrox_write_csr(ndev, offset, drbl.value); in nitrox_config_aqm_rings()
375 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
379 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
384 qsize.host_queue_size = ndev->qlen; in nitrox_config_aqm_rings()
385 nitrox_write_csr(ndev, offset, qsize.value); in nitrox_config_aqm_rings()
391 nitrox_write_csr(ndev, offset, cmp_thr.value); in nitrox_config_aqm_rings()
394 enable_aqm_ring(ndev, ring); in nitrox_config_aqm_rings()
398 static void enable_aqm_interrupts(struct nitrox_device *ndev) in enable_aqm_interrupts() argument
401 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
403 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
405 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
406 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
407 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
411 void nitrox_config_aqm_unit(struct nitrox_device *ndev) in nitrox_config_aqm_unit() argument
414 nitrox_config_aqm_rings(ndev); in nitrox_config_aqm_unit()
417 enable_aqm_interrupts(ndev); in nitrox_config_aqm_unit()
420 void nitrox_config_pom_unit(struct nitrox_device *ndev) in nitrox_config_pom_unit() argument
428 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value); in nitrox_config_pom_unit()
431 for (i = 0; i < ndev->hw.se_cores; i++) in nitrox_config_pom_unit()
432 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i)); in nitrox_config_pom_unit()
439 void nitrox_config_rand_unit(struct nitrox_device *ndev) in nitrox_config_rand_unit() argument
445 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_rand_unit()
448 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
451 void nitrox_config_efl_unit(struct nitrox_device *ndev) in nitrox_config_efl_unit() argument
465 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
468 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
470 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
474 void nitrox_config_bmi_unit(struct nitrox_device *ndev) in nitrox_config_bmi_unit() argument
482 bmi_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmi_unit()
486 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
494 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
497 void nitrox_config_bmo_unit(struct nitrox_device *ndev) in nitrox_config_bmo_unit() argument
504 bmo_ctl2.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmo_unit()
506 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
509 void invalidate_lbc(struct nitrox_device *ndev) in invalidate_lbc() argument
518 lbc_ctl.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
520 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
524 lbc_stat.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
531 void nitrox_config_lbc_unit(struct nitrox_device *ndev) in nitrox_config_lbc_unit() argument
536 invalidate_lbc(ndev); in nitrox_config_lbc_unit()
545 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
548 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
550 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
553 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
555 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
558 void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode) in config_nps_core_vfcfg_mode() argument
562 vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG); in config_nps_core_vfcfg_mode()
565 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value); in config_nps_core_vfcfg_mode()
607 void nitrox_get_hwinfo(struct nitrox_device *ndev) in nitrox_get_hwinfo() argument
618 rst_boot.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
619 ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK; in nitrox_get_hwinfo()
623 emu_fuse.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
626 ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores; in nitrox_get_hwinfo()
628 ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores; in nitrox_get_hwinfo()
633 fus_dat1.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
636 ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores; in nitrox_get_hwinfo()
643 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores), in nitrox_get_hwinfo()
644 ndev->hw.freq, in nitrox_get_hwinfo()
645 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq), in nitrox_get_hwinfo()
646 ndev->hw.revision_id); in nitrox_get_hwinfo()
649 strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname)); in nitrox_get_hwinfo()
652 void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev) in enable_pf2vf_mbox_interrupts() argument
659 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
663 nitrox_write_csr(ndev, reg_addr, value); in enable_pf2vf_mbox_interrupts()
666 void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev) in disable_pf2vf_mbox_interrupts() argument
673 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()
677 nitrox_write_csr(ndev, reg_addr, value); in disable_pf2vf_mbox_interrupts()