23 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)  in qce_write()  function
34 		qce_write(qce, offset + i * sizeof(u32), val[i]);  in qce_write_array()
43 		qce_write(qce, offset + i * sizeof(u32), 0);  in qce_clear_array()
86 	qce_write(qce, REG_STATUS, 0);  in qce_setup_config()
87 	qce_write(qce, REG_CONFIG, config);  in qce_setup_config()
92 	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));  in qce_crypto_go()
164 		qce_write(qce, REG_AUTH_SEG_CFG, 0);  in qce_setup_regs_ahash()
165 		qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
166 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);  in qce_setup_regs_ahash()
212 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ahash()
213 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
214 	qce_write(qce, REG_AUTH_SEG_START, 0);  in qce_setup_regs_ahash()
215 	qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
216 	qce_write(qce, REG_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
220 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ahash()
305 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);  in qce_xtskey()
334 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_skcipher()
367 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);  in qce_setup_regs_skcipher()
368 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_skcipher()
369 	qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);  in qce_setup_regs_skcipher()
372 		qce_write(qce, REG_CNTR_MASK, ~0);  in qce_setup_regs_skcipher()
373 		qce_write(qce, REG_CNTR_MASK0, ~0);  in qce_setup_regs_skcipher()
374 		qce_write(qce, REG_CNTR_MASK1, ~0);  in qce_setup_regs_skcipher()
375 		qce_write(qce, REG_CNTR_MASK2, ~0);  in qce_setup_regs_skcipher()
378 	qce_write(qce, REG_SEG_SIZE, totallen);  in qce_setup_regs_skcipher()
382 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_skcipher()