Lines Matching refs:chan
216 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; member
219 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) in stm32_dma_get_dev() argument
221 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
227 return container_of(c, struct stm32_dma_chan, vchan.chan); in to_stm32_dma_chan()
235 static struct device *chan2dev(struct stm32_dma_chan *chan) in chan2dev() argument
237 return &chan->vchan.chan.dev->device; in chan2dev()
250 static int stm32_dma_get_width(struct stm32_dma_chan *chan, in stm32_dma_get_width() argument
261 dev_err(chan2dev(chan), "Dma bus width not supported\n"); in stm32_dma_get_width()
344 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) in stm32_dma_get_burst() argument
357 dev_err(chan2dev(chan), "Dma burst size not supported\n"); in stm32_dma_get_burst()
362 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, in stm32_dma_set_fifo_config() argument
365 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
366 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
370 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
373 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
380 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_slave_config() local
382 memcpy(&chan->dma_sconfig, config, sizeof(*config)); in stm32_dma_slave_config()
384 chan->config_init = true; in stm32_dma_slave_config()
389 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) in stm32_dma_irq_status() argument
391 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_status()
402 if (chan->id & 4) in stm32_dma_irq_status()
407 flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); in stm32_dma_irq_status()
412 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) in stm32_dma_irq_clear() argument
414 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_irq_clear()
425 dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); in stm32_dma_irq_clear()
427 if (chan->id & 4) in stm32_dma_irq_clear()
433 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) in stm32_dma_disable_chan() argument
435 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_disable_chan()
438 id = chan->id; in stm32_dma_disable_chan()
454 static void stm32_dma_stop(struct stm32_dma_chan *chan) in stm32_dma_stop() argument
456 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_stop()
461 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
463 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
464 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_stop()
466 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
469 ret = stm32_dma_disable_chan(chan); in stm32_dma_stop()
474 status = stm32_dma_irq_status(chan); in stm32_dma_stop()
476 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", in stm32_dma_stop()
478 stm32_dma_irq_clear(chan, status); in stm32_dma_stop()
481 chan->busy = false; in stm32_dma_stop()
486 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_terminate_all() local
490 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
492 if (chan->desc) { in stm32_dma_terminate_all()
493 vchan_terminate_vdesc(&chan->desc->vdesc); in stm32_dma_terminate_all()
494 if (chan->busy) in stm32_dma_terminate_all()
495 stm32_dma_stop(chan); in stm32_dma_terminate_all()
496 chan->desc = NULL; in stm32_dma_terminate_all()
499 vchan_get_all_descriptors(&chan->vchan, &head); in stm32_dma_terminate_all()
500 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
501 vchan_dma_desc_free_list(&chan->vchan, &head); in stm32_dma_terminate_all()
508 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_synchronize() local
510 vchan_synchronize(&chan->vchan); in stm32_dma_synchronize()
513 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) in stm32_dma_dump_reg() argument
515 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_dump_reg()
516 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg()
517 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_dump_reg()
518 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); in stm32_dma_dump_reg()
519 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); in stm32_dma_dump_reg()
520 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); in stm32_dma_dump_reg()
521 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_dump_reg()
523 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); in stm32_dma_dump_reg()
524 dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); in stm32_dma_dump_reg()
525 dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); in stm32_dma_dump_reg()
526 dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); in stm32_dma_dump_reg()
527 dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); in stm32_dma_dump_reg()
528 dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); in stm32_dma_dump_reg()
531 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
533 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) in stm32_dma_start_transfer() argument
535 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_start_transfer()
542 ret = stm32_dma_disable_chan(chan); in stm32_dma_start_transfer()
546 if (!chan->desc) { in stm32_dma_start_transfer()
547 vdesc = vchan_next_desc(&chan->vchan); in stm32_dma_start_transfer()
553 chan->desc = to_stm32_dma_desc(vdesc); in stm32_dma_start_transfer()
554 chan->next_sg = 0; in stm32_dma_start_transfer()
557 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_start_transfer()
558 chan->next_sg = 0; in stm32_dma_start_transfer()
560 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_start_transfer()
564 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
565 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
566 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
567 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
568 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
569 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
571 chan->next_sg++; in stm32_dma_start_transfer()
574 status = stm32_dma_irq_status(chan); in stm32_dma_start_transfer()
576 stm32_dma_irq_clear(chan, status); in stm32_dma_start_transfer()
578 if (chan->desc->cyclic) in stm32_dma_start_transfer()
579 stm32_dma_configure_next_sg(chan); in stm32_dma_start_transfer()
581 stm32_dma_dump_reg(chan); in stm32_dma_start_transfer()
585 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
587 chan->busy = true; in stm32_dma_start_transfer()
589 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); in stm32_dma_start_transfer()
592 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) in stm32_dma_configure_next_sg() argument
594 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_configure_next_sg()
598 id = chan->id; in stm32_dma_configure_next_sg()
602 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_configure_next_sg()
603 chan->next_sg = 0; in stm32_dma_configure_next_sg()
605 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_configure_next_sg()
610 dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", in stm32_dma_configure_next_sg()
615 dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", in stm32_dma_configure_next_sg()
621 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) in stm32_dma_handle_chan_done() argument
623 if (chan->desc) { in stm32_dma_handle_chan_done()
624 if (chan->desc->cyclic) { in stm32_dma_handle_chan_done()
625 vchan_cyclic_callback(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
626 chan->next_sg++; in stm32_dma_handle_chan_done()
627 stm32_dma_configure_next_sg(chan); in stm32_dma_handle_chan_done()
629 chan->busy = false; in stm32_dma_handle_chan_done()
630 if (chan->next_sg == chan->desc->num_sgs) { in stm32_dma_handle_chan_done()
631 vchan_cookie_complete(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
632 chan->desc = NULL; in stm32_dma_handle_chan_done()
634 stm32_dma_start_transfer(chan); in stm32_dma_handle_chan_done()
641 struct stm32_dma_chan *chan = devid; in stm32_dma_chan_irq() local
642 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_chan_irq()
645 spin_lock(&chan->vchan.lock); in stm32_dma_chan_irq()
647 status = stm32_dma_irq_status(chan); in stm32_dma_chan_irq()
648 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
649 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_chan_irq()
652 stm32_dma_irq_clear(chan, STM32_DMA_TCI); in stm32_dma_chan_irq()
654 stm32_dma_handle_chan_done(chan); in stm32_dma_chan_irq()
658 stm32_dma_irq_clear(chan, STM32_DMA_HTI); in stm32_dma_chan_irq()
662 stm32_dma_irq_clear(chan, STM32_DMA_FEI); in stm32_dma_chan_irq()
666 dev_err(chan2dev(chan), "FIFO Error\n"); in stm32_dma_chan_irq()
668 dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); in stm32_dma_chan_irq()
672 stm32_dma_irq_clear(chan, STM32_DMA_DMEI); in stm32_dma_chan_irq()
675 dev_dbg(chan2dev(chan), "Direct mode overrun\n"); in stm32_dma_chan_irq()
678 stm32_dma_irq_clear(chan, status); in stm32_dma_chan_irq()
679 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); in stm32_dma_chan_irq()
681 dev_err(chan2dev(chan), "chan disabled by HW\n"); in stm32_dma_chan_irq()
684 spin_unlock(&chan->vchan.lock); in stm32_dma_chan_irq()
691 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_issue_pending() local
694 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
695 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { in stm32_dma_issue_pending()
696 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); in stm32_dma_issue_pending()
697 stm32_dma_start_transfer(chan); in stm32_dma_issue_pending()
700 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
703 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, in stm32_dma_set_xfer_param() argument
714 src_addr_width = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
715 dst_addr_width = chan->dma_sconfig.dst_addr_width; in stm32_dma_set_xfer_param()
716 src_maxburst = chan->dma_sconfig.src_maxburst; in stm32_dma_set_xfer_param()
717 dst_maxburst = chan->dma_sconfig.dst_maxburst; in stm32_dma_set_xfer_param()
718 fifoth = chan->threshold; in stm32_dma_set_xfer_param()
723 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); in stm32_dma_set_xfer_param()
733 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); in stm32_dma_set_xfer_param()
739 chan->mem_width = src_addr_width; in stm32_dma_set_xfer_param()
740 src_bus_width = stm32_dma_get_width(chan, src_addr_width); in stm32_dma_set_xfer_param()
750 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); in stm32_dma_set_xfer_param()
761 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
763 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); in stm32_dma_set_xfer_param()
766 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; in stm32_dma_set_xfer_param()
772 src_bus_width = stm32_dma_get_width(chan, src_addr_width); in stm32_dma_set_xfer_param()
781 chan->mem_burst = src_best_burst; in stm32_dma_set_xfer_param()
782 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); in stm32_dma_set_xfer_param()
788 chan->mem_width = dst_addr_width; in stm32_dma_set_xfer_param()
789 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); in stm32_dma_set_xfer_param()
799 chan->mem_burst = dst_best_burst; in stm32_dma_set_xfer_param()
800 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); in stm32_dma_set_xfer_param()
811 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
813 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); in stm32_dma_set_xfer_param()
816 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; in stm32_dma_set_xfer_param()
817 *buswidth = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
821 dev_err(chan2dev(chan), "Dma direction is not supported\n"); in stm32_dma_set_xfer_param()
825 stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); in stm32_dma_set_xfer_param()
828 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | in stm32_dma_set_xfer_param()
831 chan->chan_reg.dma_scr |= dma_scr; in stm32_dma_set_xfer_param()
846 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_slave_sg() local
853 if (!chan->config_init) { in stm32_dma_prep_slave_sg()
854 dev_err(chan2dev(chan), "dma channel is not configured\n"); in stm32_dma_prep_slave_sg()
859 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); in stm32_dma_prep_slave_sg()
868 if (chan->dma_sconfig.device_fc) in stm32_dma_prep_slave_sg()
869 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
871 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
874 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, in stm32_dma_prep_slave_sg()
883 dev_err(chan2dev(chan), "nb items not supported\n"); in stm32_dma_prep_slave_sg()
888 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_slave_sg()
889 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_slave_sg()
890 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_slave_sg()
899 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_slave_sg()
911 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_dma_cyclic() local
918 dev_err(chan2dev(chan), "Invalid buffer/period len\n"); in stm32_dma_prep_dma_cyclic()
922 if (!chan->config_init) { in stm32_dma_prep_dma_cyclic()
923 dev_err(chan2dev(chan), "dma channel is not configured\n"); in stm32_dma_prep_dma_cyclic()
928 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); in stm32_dma_prep_dma_cyclic()
938 if (chan->busy) { in stm32_dma_prep_dma_cyclic()
939 dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); in stm32_dma_prep_dma_cyclic()
943 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len); in stm32_dma_prep_dma_cyclic()
949 dev_err(chan2dev(chan), "number of items not supported\n"); in stm32_dma_prep_dma_cyclic()
955 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_prep_dma_cyclic()
957 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_dma_cyclic()
960 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_dma_cyclic()
972 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_dma_cyclic()
973 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_dma_cyclic()
974 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_dma_cyclic()
984 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_cyclic()
991 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_prep_dma_memcpy() local
1003 threshold = chan->threshold; in stm32_dma_prep_dma_memcpy()
1013 dma_burst = stm32_dma_get_burst(chan, best_burst); in stm32_dma_prep_dma_memcpy()
1036 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_memcpy()
1039 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) in stm32_dma_get_remaining_bytes() argument
1042 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_get_remaining_bytes()
1044 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
1046 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_get_remaining_bytes()
1063 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) in stm32_dma_is_current_sg() argument
1065 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_is_current_sg()
1069 id = chan->id; in stm32_dma_is_current_sg()
1075 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_is_current_sg()
1087 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, in stm32_dma_desc_residue() argument
1094 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_desc_residue()
1122 residue = stm32_dma_get_remaining_bytes(chan); in stm32_dma_desc_residue()
1124 if (!stm32_dma_is_current_sg(chan)) { in stm32_dma_desc_residue()
1126 if (n_sg == chan->desc->num_sgs) in stm32_dma_desc_residue()
1138 if (!chan->desc->cyclic || n_sg != 0) in stm32_dma_desc_residue()
1142 if (!chan->mem_burst) in stm32_dma_desc_residue()
1145 burst_size = chan->mem_burst * chan->mem_width; in stm32_dma_desc_residue()
1157 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_tx_status() local
1167 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1168 vdesc = vchan_find_desc(&chan->vchan, cookie); in stm32_dma_tx_status()
1169 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) in stm32_dma_tx_status()
1170 residue = stm32_dma_desc_residue(chan, chan->desc, in stm32_dma_tx_status()
1171 chan->next_sg); in stm32_dma_tx_status()
1173 residue = stm32_dma_desc_residue(chan, in stm32_dma_tx_status()
1177 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1184 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_alloc_chan_resources() local
1185 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_alloc_chan_resources()
1188 chan->config_init = false; in stm32_dma_alloc_chan_resources()
1194 ret = stm32_dma_disable_chan(chan); in stm32_dma_alloc_chan_resources()
1203 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); in stm32_dma_free_chan_resources() local
1204 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); in stm32_dma_free_chan_resources()
1207 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); in stm32_dma_free_chan_resources()
1209 if (chan->busy) { in stm32_dma_free_chan_resources()
1210 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1211 stm32_dma_stop(chan); in stm32_dma_free_chan_resources()
1212 chan->desc = NULL; in stm32_dma_free_chan_resources()
1213 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1226 static void stm32_dma_set_config(struct stm32_dma_chan *chan, in stm32_dma_set_config() argument
1229 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_set_config()
1231 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; in stm32_dma_set_config()
1232 chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); in stm32_dma_set_config()
1235 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; in stm32_dma_set_config()
1237 chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); in stm32_dma_set_config()
1239 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; in stm32_dma_set_config()
1248 struct stm32_dma_chan *chan; in stm32_dma_of_xlate() local
1267 chan = &dmadev->chan[cfg.channel_id]; in stm32_dma_of_xlate()
1269 c = dma_get_slave_channel(&chan->vchan.chan); in stm32_dma_of_xlate()
1275 stm32_dma_set_config(chan, &cfg); in stm32_dma_of_xlate()
1288 struct stm32_dma_chan *chan; in stm32_dma_probe() local
1372 chan = &dmadev->chan[i]; in stm32_dma_probe()
1373 chan->id = i; in stm32_dma_probe()
1374 chan->vchan.desc_free = stm32_dma_desc_free; in stm32_dma_probe()
1375 vchan_init(&chan->vchan, dd); in stm32_dma_probe()
1383 chan = &dmadev->chan[i]; in stm32_dma_probe()
1387 chan->irq = ret; in stm32_dma_probe()
1389 ret = devm_request_irq(&pdev->dev, chan->irq, in stm32_dma_probe()
1391 dev_name(chan2dev(chan)), chan); in stm32_dma_probe()