Lines Matching refs:pvt
178 static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset) in dmc520_read_reg() argument
180 return readl(pvt->reg_base + offset); in dmc520_read_reg()
183 static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset) in dmc520_write_reg() argument
185 writel(val, pvt->reg_base + offset); in dmc520_write_reg()
200 static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt, in dmc520_get_dram_ecc_error_count() argument
212 err_low = dmc520_read_reg(pvt, reg_offset_low); in dmc520_get_dram_ecc_error_count()
213 err_high = dmc520_read_reg(pvt, reg_offset_high); in dmc520_get_dram_ecc_error_count()
215 dmc520_write_reg(pvt, 0, reg_offset_low); in dmc520_get_dram_ecc_error_count()
216 dmc520_write_reg(pvt, 0, reg_offset_high); in dmc520_get_dram_ecc_error_count()
224 static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt, in dmc520_get_dram_ecc_error_info() argument
237 reg_val_low = dmc520_read_reg(pvt, reg_offset_low); in dmc520_get_dram_ecc_error_info()
238 reg_val_high = dmc520_read_reg(pvt, reg_offset_high); in dmc520_get_dram_ecc_error_info()
260 static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt) in dmc520_get_scrub_type() argument
265 reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW); in dmc520_get_scrub_type()
276 static u32 dmc520_get_memory_width(struct dmc520_edac *pvt) in dmc520_get_memory_width() argument
282 reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL); in dmc520_get_memory_width()
292 static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt) in dmc520_get_mtype() argument
298 reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); in dmc520_get_mtype()
314 static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt) in dmc520_get_dtype() argument
320 reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); in dmc520_get_dtype()
350 static u64 dmc520_get_rank_size(struct dmc520_edac *pvt) in dmc520_get_rank_size() argument
354 reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW); in dmc520_get_rank_size()
362 return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits); in dmc520_get_rank_size()
368 struct dmc520_edac *pvt = mci->pvt_info; in dmc520_handle_dram_ecc_errors() local
373 dmc520_get_dram_ecc_error_info(pvt, is_ce, &info); in dmc520_handle_dram_ecc_errors()
375 cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce); in dmc520_handle_dram_ecc_errors()
384 spin_lock(&pvt->error_lock); in dmc520_handle_dram_ecc_errors()
389 spin_unlock(&pvt->error_lock); in dmc520_handle_dram_ecc_errors()
395 struct dmc520_edac *pvt = mci->pvt_info; in dmc520_edac_dram_ecc_isr() local
402 dmc520_write_reg(pvt, i_mask, REG_OFFSET_INTERRUPT_CLR); in dmc520_edac_dram_ecc_isr()
410 struct dmc520_edac *pvt = mci->pvt_info; in dmc520_edac_dram_all_isr() local
414 status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS); in dmc520_edac_dram_all_isr()
430 struct dmc520_edac *pvt = mci->pvt_info; in dmc520_isr() local
435 if (pvt->irqs[idx] == irq) { in dmc520_isr()
436 mask = pvt->masks[idx]; in dmc520_isr()
445 struct dmc520_edac *pvt = mci->pvt_info; in dmc520_init_csrow() local
454 dt = dmc520_get_dtype(pvt); in dmc520_init_csrow()
455 mt = dmc520_get_mtype(pvt); in dmc520_init_csrow()
456 rs = dmc520_get_rank_size(pvt); in dmc520_init_csrow()
464 dimm->grain = pvt->mem_width_in_bytes; in dmc520_init_csrow()
479 struct dmc520_edac *pvt = NULL; in dmc520_edac_probe() local
520 mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt)); in dmc520_edac_probe()
528 pvt = mci->pvt_info; in dmc520_edac_probe()
530 pvt->reg_base = reg_base; in dmc520_edac_probe()
531 spin_lock_init(&pvt->error_lock); in dmc520_edac_probe()
532 memcpy(pvt->irqs, irqs, sizeof(irqs)); in dmc520_edac_probe()
533 memcpy(pvt->masks, masks, sizeof(masks)); in dmc520_edac_probe()
542 mci->scrub_mode = dmc520_get_scrub_type(pvt); in dmc520_edac_probe()
549 pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt); in dmc520_edac_probe()
554 reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL); in dmc520_edac_probe()
555 dmc520_write_reg(pvt, reg_val & (~irq_mask_all), in dmc520_edac_probe()
557 dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR); in dmc520_edac_probe()
576 dmc520_get_dram_ecc_error_count(pvt, true); in dmc520_edac_probe()
579 dmc520_get_dram_ecc_error_count(pvt, false); in dmc520_edac_probe()
589 dmc520_write_reg(pvt, reg_val | irq_mask_all, in dmc520_edac_probe()
597 devm_free_irq(&pdev->dev, pvt->irqs[idx], mci); in dmc520_edac_probe()
609 struct dmc520_edac *pvt; in dmc520_edac_remove() local
612 pvt = mci->pvt_info; in dmc520_edac_remove()
615 reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL); in dmc520_edac_remove()
616 dmc520_write_reg(pvt, reg_val & (~irq_mask_all), in dmc520_edac_remove()
621 if (pvt->irqs[idx] >= 0) { in dmc520_edac_remove()
622 irq_mask_all |= pvt->masks[idx]; in dmc520_edac_remove()
623 devm_free_irq(&pdev->dev, pvt->irqs[idx], mci); in dmc520_edac_remove()