34 static const u32 ctrl_base = 0x80000000;  variable
220 		opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0);  in check_errors()
221 		opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0);  in check_errors()
222 		opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0);  in check_errors()
234 		ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0,  in check_errors()
332 		ret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg);  in aspeed_master_link_enable()
336 	ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);  in aspeed_master_link_enable()
393 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
398 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
401 	opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);  in aspeed_master_init()
409 	opb_writel(aspeed, ctrl_base + FSI_MMODE, reg);  in aspeed_master_init()
412 	opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);  in aspeed_master_init()
415 	opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);  in aspeed_master_init()
420 	opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);  in aspeed_master_init()
422 	opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);  in aspeed_master_init()
425 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);  in aspeed_master_init()
427 	opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);  in aspeed_master_init()
431 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);  in aspeed_master_init()
434 	opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);  in aspeed_master_init()
449 	opb_writel(aspeed, ctrl_base + FSI_MRESP0, cpu_to_be32(FSI_MRESP_RST_ALL_MASTER));  in cfam_reset_store()
575 	writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);  in fsi_master_aspeed_probe()
592 	rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);  in fsi_master_aspeed_probe()