Lines Matching defs:amdgpu_gfx_config

140 struct amdgpu_gfx_config {  struct
141 	unsigned max_shader_engines;
142 	unsigned max_tile_pipes;
143 	unsigned max_cu_per_sh;
144 	unsigned max_sh_per_se;
145 	unsigned max_backends_per_se;
146 	unsigned max_texture_channel_caches;
147 	unsigned max_gprs;
148 	unsigned max_gs_threads;
149 	unsigned max_hw_contexts;
150 	unsigned sc_prim_fifo_size_frontend;
151 	unsigned sc_prim_fifo_size_backend;
152 	unsigned sc_hiz_tile_fifo_size;
153 	unsigned sc_earlyz_tile_fifo_size;
155 	unsigned num_tile_pipes;
156 	unsigned backend_enable_mask;
157 	unsigned mem_max_burst_length_bytes;
158 	unsigned mem_row_size_in_kb;
159 	unsigned shader_engine_tile_size;
160 	unsigned num_gpus;
161 	unsigned multi_gpu_tile_size;
162 	unsigned mc_arb_ramcfg;
163 	unsigned num_banks;
164 	unsigned num_ranks;
165 	unsigned gb_addr_config;
166 	unsigned num_rbs;
167 	unsigned gs_vgt_table_depth;
168 	unsigned gs_prim_buffer_depth;
170 	uint32_t tile_mode_array[32];
171 	uint32_t macrotile_mode_array[16];
173 	struct gb_addr_config gb_addr_config_fields;
174 	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
177 	uint32_t double_offchip_lds_buf;
179 	uint32_t db_debug2;
181 	uint32_t num_sc_per_sh;
182 	uint32_t num_packer_per_sc;
183 	uint32_t pa_sc_tile_steering_override;
184 	uint64_t tcc_disabled_mask;