Lines Matching refs:vcn
80 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()
81 adev->vcn.harvest_config = 0; in vcn_v2_5_early_init()
82 adev->vcn.num_enc_rings = 1; in vcn_v2_5_early_init()
86 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS; in vcn_v2_5_early_init()
87 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
90 adev->vcn.harvest_config |= 1 << i; in vcn_v2_5_early_init()
92 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | in vcn_v2_5_early_init()
97 adev->vcn.num_enc_rings = 2; in vcn_v2_5_early_init()
120 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
121 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
125 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
130 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
132 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
144 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v2_5_sw_init()
146 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; in vcn_v2_5_sw_init()
150 if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) { in vcn_v2_5_sw_init()
152 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; in vcn_v2_5_sw_init()
163 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
166 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
168 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
169 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
170 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
171 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
172 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
173 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
175 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
176 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
177 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
178 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
179 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
180 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
181 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
182 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
183 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
184 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
186 ring = &adev->vcn.inst[j].ring_dec; in vcn_v2_5_sw_init()
189 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + in vcn_v2_5_sw_init()
192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, in vcn_v2_5_sw_init()
197 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
198 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_sw_init()
201 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + in vcn_v2_5_sw_init()
206 &adev->vcn.inst[j].irq, 0, in vcn_v2_5_sw_init()
212 fw_shared = adev->vcn.inst[j].fw_shared_cpu_addr; in vcn_v2_5_sw_init()
223 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; in vcn_v2_5_sw_init()
242 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()
243 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_sw_fini()
245 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; in vcn_v2_5_sw_fini()
280 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()
281 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_hw_init()
285 adev->vcn.inst[j].ring_enc[0].sched.ready = true; in vcn_v2_5_hw_init()
286 adev->vcn.inst[j].ring_enc[1].sched.ready = false; in vcn_v2_5_hw_init()
287 adev->vcn.inst[j].ring_enc[2].sched.ready = false; in vcn_v2_5_hw_init()
288 adev->vcn.inst[j].ring_dec.sched.ready = true; in vcn_v2_5_hw_init()
291 ring = &adev->vcn.inst[j].ring_dec; in vcn_v2_5_hw_init()
300 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_hw_init()
301 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_hw_init()
329 cancel_delayed_work_sync(&adev->vcn.idle_work); in vcn_v2_5_hw_fini()
331 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()
332 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_hw_fini()
336 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v2_5_hw_fini()
395 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume()
399 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()
400 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_mc_resume()
412 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
414 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
423 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
425 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
431 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
433 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
439 lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr)); in vcn_v2_5_mc_resume()
441 upper_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr)); in vcn_v2_5_mc_resume()
450 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
476 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
479 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
517 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
520 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
529 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
532 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
556 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()
557 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_disable_clock_gating()
721 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_enable_clock_gating()
722 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_enable_clock_gating()
773 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; in vcn_v2_5_start_dpg_mode()
787 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_add… in vcn_v2_5_start_dpg_mode()
865 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in vcn_v2_5_start_dpg_mode()
866 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - in vcn_v2_5_start_dpg_mode()
867 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); in vcn_v2_5_start_dpg_mode()
869 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v2_5_start_dpg_mode()
924 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
925 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
928 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); in vcn_v2_5_start()
947 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
948 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
996 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
997 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; in vcn_v2_5_start()
998 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
1061 ring = &adev->vcn.inst[i].ring_dec; in vcn_v2_5_start()
1087 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_start()
1096 ring = &adev->vcn.inst[i].ring_enc[1]; in vcn_v2_5_start()
1183 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_sriov_start()
1194 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_sriov_start()
1212 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1216 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1229 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_sriov_start()
1233 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_sriov_start()
1243 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + in vcn_v2_5_sriov_start()
1248 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + in vcn_v2_5_sriov_start()
1257 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_sriov_start()
1270 ring = &adev->vcn.inst[i].ring_dec; in vcn_v2_5_sriov_start()
1337 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_stop()
1338 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_stop()
1408 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_5_pause_dpg_mode()
1410 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_5_pause_dpg_mode()
1419 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; in vcn_v2_5_pause_dpg_mode()
1437 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v2_5_pause_dpg_mode()
1447 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; in vcn_v2_5_pause_dpg_mode()
1469 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_5_pause_dpg_mode()
1566 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v2_5_enc_ring_get_rptr()
1583 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_get_wptr()
1607 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_set_wptr()
1658 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_dec_ring_funcs()
1659 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_dec_ring_funcs()
1661 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; in vcn_v2_5_set_dec_ring_funcs()
1662 adev->vcn.inst[i].ring_dec.me = i; in vcn_v2_5_set_dec_ring_funcs()
1671 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_set_enc_ring_funcs()
1672 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_set_enc_ring_funcs()
1674 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_set_enc_ring_funcs()
1675 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; in vcn_v2_5_set_enc_ring_funcs()
1676 adev->vcn.inst[j].ring_enc[i].me = j; in vcn_v2_5_set_enc_ring_funcs()
1687 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_is_idle()
1688 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_is_idle()
1701 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_wait_for_idle()
1702 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_wait_for_idle()
1742 if(state == adev->vcn.cur_state) in vcn_v2_5_set_powergating_state()
1751 adev->vcn.cur_state = state; in vcn_v2_5_set_powergating_state()
1786 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); in vcn_v2_5_process_interrupt()
1789 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v2_5_process_interrupt()
1792 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); in vcn_v2_5_process_interrupt()
1812 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_irq_funcs()
1813 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_irq_funcs()
1815 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; in vcn_v2_5_set_irq_funcs()
1816 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; in vcn_v2_5_set_irq_funcs()