277 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_init_blank()
568 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_plane_atomic_disable()
644 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_enable_stream_timing()
694 	if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal)))  in dcn20_enable_stream_timing()
695 		dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx);  in dcn20_enable_stream_timing()
893 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_set_input_transfer_func()
1094 	dcn20_power_on_plane(dc->hwseq, pipe_ctx);  in dcn20_enable_plane()
1375 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_update_dchubp_dpp()
1573 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_program_pipe()
1648 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_program_front_end_for_ctx()
1726 	struct dce_hwseq *hwseq = dc->hwseq;  in dcn20_post_unlock_program_front_end()  local
1754 	if (hwseq->wa.DEGVIDCN21)  in dcn20_post_unlock_program_front_end()
1759 	if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) {  in dcn20_post_unlock_program_front_end()
1768 			hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true;  in dcn20_post_unlock_program_front_end()
1769 …hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->…  in dcn20_post_unlock_program_front_end()
1815 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_update_bandwidth()
1935 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_disable_stream_gating()
1950 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_enable_stream_gating()
2083 	struct dce_hwseq *hws = link->dc->hwseq;  in dcn20_unblank_stream()
2202 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_reset_hw_ctx_wrap()
2253 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_update_mpcc()
2421 	struct dce_hwseq *hws = dc->hwseq;  in dcn20_fpga_init_hw()