Lines Matching refs:level
1090 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument
1110 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511; in g4x_plane_fifo_size()
1112 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0; in g4x_plane_fifo_size()
1119 static int g4x_fbc_fifo_size(int level) in g4x_fbc_fifo_size() argument
1121 switch (level) { in g4x_fbc_fifo_size()
1127 MISSING_CASE(level); in g4x_fbc_fifo_size()
1134 int level) in g4x_compute_wm() argument
1140 unsigned int latency = dev_priv->wm.pri_latency[level] * 10; in g4x_compute_wm()
1163 level != G4X_WM_LEVEL_NORMAL) in g4x_compute_wm()
1174 level == G4X_WM_LEVEL_NORMAL) { in g4x_compute_wm()
1185 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), in g4x_compute_wm()
1194 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument
1199 for (; level < intel_wm_num_levels(dev_priv); level++) { in g4x_raw_plane_wm_set()
1200 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_set()
1210 int level, u16 value) in g4x_raw_fbc_wm_set() argument
1216 level = max(level, G4X_WM_LEVEL_SR); in g4x_raw_fbc_wm_set()
1218 for (; level < intel_wm_num_levels(dev_priv); level++) { in g4x_raw_fbc_wm_set()
1219 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_fbc_wm_set()
1240 int level; in g4x_raw_plane_wm_compute() local
1249 for (level = 0; level < num_levels; level++) { in g4x_raw_plane_wm_compute()
1250 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_compute()
1253 wm = g4x_compute_wm(crtc_state, plane_state, level); in g4x_raw_plane_wm_compute()
1254 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute()
1263 level == G4X_WM_LEVEL_NORMAL) in g4x_raw_plane_wm_compute()
1268 max_wm = g4x_fbc_fifo_size(level); in g4x_raw_plane_wm_compute()
1282 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); in g4x_raw_plane_wm_compute()
1285 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); in g4x_raw_plane_wm_compute()
1307 enum plane_id plane_id, int level) in g4x_raw_plane_wm_is_valid() argument
1309 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_is_valid()
1311 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_is_valid()
1315 int level) in g4x_raw_crtc_wm_is_valid() argument
1319 if (level > dev_priv->wm.max_level) in g4x_raw_crtc_wm_is_valid()
1322 return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && in g4x_raw_crtc_wm_is_valid()
1323 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && in g4x_raw_crtc_wm_is_valid()
1324 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); in g4x_raw_crtc_wm_is_valid()
1329 struct g4x_wm_state *wm_state, int level) in g4x_invalidate_wms() argument
1331 if (level <= G4X_WM_LEVEL_NORMAL) { in g4x_invalidate_wms()
1338 if (level <= G4X_WM_LEVEL_SR) { in g4x_invalidate_wms()
1345 if (level <= G4X_WM_LEVEL_HPLL) { in g4x_invalidate_wms()
1354 int level) in g4x_compute_fbc_en() argument
1356 if (level < G4X_WM_LEVEL_SR) in g4x_compute_fbc_en()
1359 if (level >= G4X_WM_LEVEL_SR && in g4x_compute_fbc_en()
1363 if (level >= G4X_WM_LEVEL_HPLL && in g4x_compute_fbc_en()
1383 int i, level; in g4x_compute_pipe_wm() local
1400 level = G4X_WM_LEVEL_NORMAL; in g4x_compute_pipe_wm()
1401 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) in g4x_compute_pipe_wm()
1404 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1408 level = G4X_WM_LEVEL_SR; in g4x_compute_pipe_wm()
1409 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) in g4x_compute_pipe_wm()
1412 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1419 level = G4X_WM_LEVEL_HPLL; in g4x_compute_pipe_wm()
1420 if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) in g4x_compute_pipe_wm()
1423 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1430 level++; in g4x_compute_pipe_wm()
1433 if (level == G4X_WM_LEVEL_NORMAL) in g4x_compute_pipe_wm()
1437 g4x_invalidate_wms(crtc, wm_state, level); in g4x_compute_pipe_wm()
1446 wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1); in g4x_compute_pipe_wm()
1659 int level) in vlv_compute_wm_level() argument
1667 if (dev_priv->wm.pri_latency[level] == 0) in vlv_compute_wm_level()
1688 dev_priv->wm.pri_latency[level] * 10); in vlv_compute_wm_level()
1785 struct vlv_wm_state *wm_state, int level) in vlv_invalidate_wms() argument
1789 for (; level < intel_wm_num_levels(dev_priv); level++) { in vlv_invalidate_wms()
1793 wm_state->wm[level].plane[plane_id] = USHRT_MAX; in vlv_invalidate_wms()
1795 wm_state->sr[level].cursor = USHRT_MAX; in vlv_invalidate_wms()
1796 wm_state->sr[level].plane = USHRT_MAX; in vlv_invalidate_wms()
1813 int level, enum plane_id plane_id, u16 value) in vlv_raw_plane_wm_set() argument
1819 for (; level < num_levels; level++) { in vlv_raw_plane_wm_set()
1820 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1836 int level; in vlv_raw_plane_wm_compute() local
1844 for (level = 0; level < num_levels; level++) { in vlv_raw_plane_wm_compute()
1845 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1846 int wm = vlv_compute_wm_level(crtc_state, plane_state, level); in vlv_raw_plane_wm_compute()
1857 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); in vlv_raw_plane_wm_compute()
1872 enum plane_id plane_id, int level) in vlv_raw_plane_wm_is_valid() argument
1875 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1882 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level) in vlv_raw_crtc_wm_is_valid() argument
1884 return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && in vlv_raw_crtc_wm_is_valid()
1885 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && in vlv_raw_crtc_wm_is_valid()
1886 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) && in vlv_raw_crtc_wm_is_valid()
1887 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); in vlv_raw_crtc_wm_is_valid()
1906 int level, ret, i; in vlv_compute_pipe_wm() local
1958 for (level = 0; level < wm_state->num_levels; level++) { in vlv_compute_pipe_wm()
1959 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_compute_pipe_wm()
1962 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level)) in vlv_compute_pipe_wm()
1966 wm_state->wm[level].plane[plane_id] = in vlv_compute_pipe_wm()
1971 wm_state->sr[level].plane = in vlv_compute_pipe_wm()
1977 wm_state->sr[level].cursor = in vlv_compute_pipe_wm()
1982 if (level == 0) in vlv_compute_pipe_wm()
1986 wm_state->num_levels = level; in vlv_compute_pipe_wm()
1989 vlv_invalidate_wms(crtc, wm_state, level); in vlv_compute_pipe_wm()
2105 int level; in vlv_compute_intermediate_wm() local
2118 for (level = 0; level < intermediate->num_levels; level++) { in vlv_compute_intermediate_wm()
2122 intermediate->wm[level].plane[plane_id] = in vlv_compute_intermediate_wm()
2123 min(optimal->wm[level].plane[plane_id], in vlv_compute_intermediate_wm()
2124 active->wm[level].plane[plane_id]); in vlv_compute_intermediate_wm()
2127 intermediate->sr[level].plane = min(optimal->sr[level].plane, in vlv_compute_intermediate_wm()
2128 active->sr[level].plane); in vlv_compute_intermediate_wm()
2129 intermediate->sr[level].cursor = min(optimal->sr[level].cursor, in vlv_compute_intermediate_wm()
2130 active->sr[level].cursor); in vlv_compute_intermediate_wm()
2133 vlv_invalidate_wms(crtc, intermediate, level); in vlv_compute_intermediate_wm()
2152 wm->level = dev_priv->wm.max_level; in vlv_merge_wm()
2165 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
2172 wm->level = VLV_WM_LEVEL_PM2; in vlv_merge_wm()
2178 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
2180 wm->sr = wm_state->sr[wm->level]; in vlv_merge_wm()
2199 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) in vlv_program_watermarks()
2202 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) in vlv_program_watermarks()
2213 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) in vlv_program_watermarks()
2216 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) in vlv_program_watermarks()
2663 int level, bool is_sprite) in ilk_plane_wm_reg_max() argument
2667 return level == 0 ? 255 : 2047; in ilk_plane_wm_reg_max()
2670 return level == 0 ? 127 : 1023; in ilk_plane_wm_reg_max()
2673 return level == 0 ? 127 : 511; in ilk_plane_wm_reg_max()
2676 return level == 0 ? 63 : 255; in ilk_plane_wm_reg_max()
2680 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) in ilk_cursor_wm_reg_max() argument
2683 return level == 0 ? 63 : 255; in ilk_cursor_wm_reg_max()
2685 return level == 0 ? 31 : 63; in ilk_cursor_wm_reg_max()
2698 int level, in ilk_plane_wm_max() argument
2710 if (level == 0 || config->num_pipes_active > 1) { in ilk_plane_wm_max()
2724 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { in ilk_plane_wm_max()
2734 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); in ilk_plane_wm_max()
2739 int level, in ilk_cursor_wm_max() argument
2743 if (level > 0 && config->num_pipes_active > 1) in ilk_cursor_wm_max()
2747 return ilk_cursor_wm_reg_max(dev_priv, level); in ilk_cursor_wm_max()
2751 int level, in ilk_compute_wm_maximums() argument
2756 max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false); in ilk_compute_wm_maximums()
2757 max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true); in ilk_compute_wm_maximums()
2758 max->cur = ilk_cursor_wm_max(dev_priv, level, config); in ilk_compute_wm_maximums()
2763 int level, in ilk_compute_wm_reg_maximums() argument
2766 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); in ilk_compute_wm_reg_maximums()
2767 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); in ilk_compute_wm_reg_maximums()
2768 max->cur = ilk_cursor_wm_reg_max(dev_priv, level); in ilk_compute_wm_reg_maximums()
2772 static bool ilk_validate_wm_level(int level, in ilk_validate_wm_level() argument
2793 if (level == 0 && !result->enable) { in ilk_validate_wm_level()
2796 level, result->pri_val, max->pri); in ilk_validate_wm_level()
2799 level, result->spr_val, max->spr); in ilk_validate_wm_level()
2802 level, result->cur_val, max->cur); in ilk_validate_wm_level()
2815 int level, in ilk_compute_wm_level() argument
2822 u16 pri_latency = dev_priv->wm.pri_latency[level]; in ilk_compute_wm_level()
2823 u16 spr_latency = dev_priv->wm.spr_latency[level]; in ilk_compute_wm_level()
2824 u16 cur_latency = dev_priv->wm.cur_latency[level]; in ilk_compute_wm_level()
2827 if (level > 0) { in ilk_compute_wm_level()
2835 pri_latency, level); in ilk_compute_wm_level()
2856 int level, max_level = ilk_wm_max_level(dev_priv); in intel_read_wm_latency() local
2902 for (level = 1; level <= max_level; level++) { in intel_read_wm_latency()
2903 if (wm[level] == 0) { in intel_read_wm_latency()
2904 for (i = level + 1; i <= max_level; i++) in intel_read_wm_latency()
2919 for (level = 1; level <= max_level; level++) { in intel_read_wm_latency()
2920 if (wm[level] == 0) in intel_read_wm_latency()
2922 wm[level] += 2; in intel_read_wm_latency()
2997 int level, max_level = ilk_wm_max_level(dev_priv); in intel_print_wm_latency() local
2999 for (level = 0; level <= max_level; level++) { in intel_print_wm_latency()
3000 unsigned int latency = wm[level]; in intel_print_wm_latency()
3005 name, level); in intel_print_wm_latency()
3015 else if (level > 0) in intel_print_wm_latency()
3019 "%s WM%d latency %u (%u.%u usec)\n", name, level, in intel_print_wm_latency()
3020 wm[level], latency / 10, latency % 10); in intel_print_wm_latency()
3027 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_increase_wm_latency() local
3033 for (level = 1; level <= max_level; level++) in ilk_increase_wm_latency()
3034 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
3152 int level, max_level = ilk_wm_max_level(dev_priv), usable_level; in ilk_compute_pipe_wm() local
3193 for (level = 1; level <= usable_level; level++) { in ilk_compute_pipe_wm()
3194 struct intel_wm_level *wm = &pipe_wm->wm[level]; in ilk_compute_pipe_wm()
3196 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state, in ilk_compute_pipe_wm()
3204 if (!ilk_validate_wm_level(level, &max, wm)) { in ilk_compute_pipe_wm()
3228 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_compute_intermediate_wm() local
3244 for (level = 0; level <= max_level; level++) { in ilk_compute_intermediate_wm()
3245 struct intel_wm_level *a_wm = &a->wm[level]; in ilk_compute_intermediate_wm()
3246 const struct intel_wm_level *b_wm = &b->wm[level]; in ilk_compute_intermediate_wm()
3278 int level, in ilk_merge_wm_level() argument
3287 const struct intel_wm_level *wm = &active->wm[level]; in ilk_merge_wm_level()
3315 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_wm_merge() local
3327 for (level = 1; level <= max_level; level++) { in ilk_wm_merge()
3328 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge()
3330 ilk_merge_wm_level(dev_priv, level, wm); in ilk_wm_merge()
3332 if (level > last_enabled_level) in ilk_wm_merge()
3334 else if (!ilk_validate_wm_level(level, max, wm)) in ilk_wm_merge()
3336 last_enabled_level = level - 1; in ilk_wm_merge()
3357 for (level = 2; level <= max_level; level++) { in ilk_wm_merge()
3358 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge()
3373 int level) in ilk_wm_lp_latency() argument
3376 return 2 * level; in ilk_wm_lp_latency()
3378 return dev_priv->wm.pri_latency[level]; in ilk_wm_lp_latency()
3387 int level, wm_lp; in ilk_compute_wm_results() local
3396 level = ilk_wm_lp_to_level(wm_lp, merged); in ilk_compute_wm_results()
3398 r = &merged->wm[level]; in ilk_compute_wm_results()
3405 (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) | in ilk_compute_wm_results()
3453 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_find_best_result() local
3456 for (level = 1; level <= max_level; level++) { in ilk_find_best_result()
3457 if (r1->wm[level].enable) in ilk_find_best_result()
3458 level1 = level; in ilk_find_best_result()
3459 if (r2->wm[level].enable) in ilk_find_best_result()
3460 level2 = level; in ilk_find_best_result()
3878 int level, latency; in skl_crtc_can_enable_sagv() local
3898 for (level = ilk_wm_max_level(dev_priv); in skl_crtc_can_enable_sagv()
3899 !wm->wm[level].plane_en; --level) in skl_crtc_can_enable_sagv()
3902 latency = dev_priv->wm.skl_latency[level]; in skl_crtc_can_enable_sagv()
4251 int level,
4262 int level, max_level = ilk_wm_max_level(dev_priv); in skl_cursor_allocation() local
4274 for (level = 0; level <= max_level; level++) { in skl_cursor_allocation()
4275 unsigned int latency = dev_priv->wm.skl_latency[level]; in skl_cursor_allocation()
4277 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm); in skl_cursor_allocation()
4782 int level) in skl_plane_wm_level() argument
4787 if (level == 0 && pipe_wm->use_sagv_wm) in skl_plane_wm_level()
4790 return &wm->wm[level]; in skl_plane_wm_level()
4808 int level; in skl_allocate_pipe_ddb() local
4878 for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) { in skl_allocate_pipe_ddb()
4885 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) { in skl_allocate_pipe_ddb()
4887 wm->wm[level].min_ddb_alloc != U16_MAX); in skl_allocate_pipe_ddb()
4894 blocks += wm->wm[level].min_ddb_alloc; in skl_allocate_pipe_ddb()
4895 blocks += wm->uv_wm[level].min_ddb_alloc; in skl_allocate_pipe_ddb()
4904 if (level < 0) { in skl_allocate_pipe_ddb()
4937 total[plane_id] = wm->wm[level].min_ddb_alloc + extra; in skl_allocate_pipe_ddb()
4948 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra; in skl_allocate_pipe_ddb()
4989 for (level++; level <= ilk_wm_max_level(dev_priv); level++) { in skl_allocate_pipe_ddb()
5006 if (wm->wm[level].min_ddb_alloc > total[plane_id] || in skl_allocate_pipe_ddb()
5007 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id]) in skl_allocate_pipe_ddb()
5008 memset(&wm->wm[level], 0, sizeof(wm->wm[level])); in skl_allocate_pipe_ddb()
5015 level == 1 && wm->wm[0].plane_en) { in skl_allocate_pipe_ddb()
5016 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; in skl_allocate_pipe_ddb()
5017 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l; in skl_allocate_pipe_ddb()
5018 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines; in skl_allocate_pipe_ddb()
5246 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level) in skl_wm_has_lines() argument
5252 return level > 0; in skl_wm_has_lines()
5256 int level, in skl_compute_plane_wm() argument
5317 if (level == 0 && wp->rc_surface) in skl_compute_plane_wm()
5322 if (level >= 1 && level <= 7) { in skl_compute_plane_wm()
5360 if (!skl_wm_has_lines(dev_priv, level)) in skl_compute_plane_wm()
5388 int level, max_level = ilk_wm_max_level(dev_priv); in skl_compute_wm_levels() local
5391 for (level = 0; level <= max_level; level++) { in skl_compute_wm_levels()
5392 struct skl_wm_level *result = &levels[level]; in skl_compute_wm_levels()
5393 unsigned int latency = dev_priv->wm.skl_latency[level]; in skl_compute_wm_levels()
5395 skl_compute_plane_wm(crtc_state, level, latency, in skl_compute_wm_levels()
5631 const struct skl_wm_level *level) in skl_write_wm_level() argument
5635 if (level->plane_en) in skl_write_wm_level()
5637 if (level->ignore_lines) in skl_write_wm_level()
5639 val |= level->plane_res_b; in skl_write_wm_level()
5640 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; in skl_write_wm_level()
5649 int level, max_level = ilk_wm_max_level(dev_priv); in skl_write_plane_wm() local
5659 for (level = 0; level <= max_level; level++) { in skl_write_plane_wm()
5662 wm_level = skl_plane_wm_level(crtc_state, plane_id, level); in skl_write_plane_wm()
5664 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), in skl_write_plane_wm()
5689 int level, max_level = ilk_wm_max_level(dev_priv); in skl_write_cursor_wm() local
5697 for (level = 0; level <= max_level; level++) { in skl_write_cursor_wm()
5700 wm_level = skl_plane_wm_level(crtc_state, plane_id, level); in skl_write_cursor_wm()
5702 skl_write_wm_level(dev_priv, CUR_WM(pipe, level), in skl_write_cursor_wm()
5723 int level, max_level = ilk_wm_max_level(dev_priv); in skl_plane_wm_equals() local
5725 for (level = 0; level <= max_level; level++) { in skl_plane_wm_equals()
5731 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) in skl_plane_wm_equals()
6222 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level) in skl_wm_level_from_reg_val() argument
6224 level->plane_en = val & PLANE_WM_EN; in skl_wm_level_from_reg_val()
6225 level->ignore_lines = val & PLANE_WM_IGNORE_LINES; in skl_wm_level_from_reg_val()
6226 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; in skl_wm_level_from_reg_val()
6227 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & in skl_wm_level_from_reg_val()
6236 int level, max_level; in skl_pipe_wm_get_hw_state() local
6245 for (level = 0; level <= max_level; level++) { in skl_pipe_wm_get_hw_state()
6247 val = I915_READ(PLANE_WM(pipe, plane_id, level)); in skl_pipe_wm_get_hw_state()
6249 val = I915_READ(CUR_WM(pipe, level)); in skl_pipe_wm_get_hw_state()
6251 skl_wm_level_from_reg_val(val, &wm->wm[level]); in skl_pipe_wm_get_hw_state()
6320 int level, max_level = ilk_wm_max_level(dev_priv); in ilk_pipe_wm_get_hw_state() local
6327 for (level = 0; level <= max_level; level++) in ilk_pipe_wm_get_hw_state()
6328 active->wm[level].enable = true; in ilk_pipe_wm_get_hw_state()
6457 int level, max_level; in g4x_wm_get_hw_state() local
6478 level = G4X_WM_LEVEL_NORMAL; in g4x_wm_get_hw_state()
6479 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6483 if (++level > max_level) in g4x_wm_get_hw_state()
6486 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6492 if (++level > max_level) in g4x_wm_get_hw_state()
6495 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
6503 g4x_raw_plane_wm_set(crtc_state, level, in g4x_wm_get_hw_state()
6505 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); in g4x_wm_get_hw_state()
6544 int level; in g4x_wm_sanitize() local
6549 for (level = 0; level < 3; level++) { in g4x_wm_sanitize()
6551 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
6558 for (level = 0; level < 3; level++) { in g4x_wm_sanitize()
6560 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
6593 wm->level = VLV_WM_LEVEL_PM2; in vlv_wm_get_hw_state()
6600 wm->level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
6624 wm->level = VLV_WM_LEVEL_DDR_DVFS; in vlv_wm_get_hw_state()
6638 int level; in vlv_wm_get_hw_state() local
6642 active->num_levels = wm->level + 1; in vlv_wm_get_hw_state()
6645 for (level = 0; level < active->num_levels; level++) { in vlv_wm_get_hw_state()
6647 &crtc_state->wm.vlv.raw[level]; in vlv_wm_get_hw_state()
6649 active->sr[level].plane = wm->sr.plane; in vlv_wm_get_hw_state()
6650 active->sr[level].cursor = wm->sr.cursor; in vlv_wm_get_hw_state()
6653 active->wm[level].plane[plane_id] = in vlv_wm_get_hw_state()
6657 vlv_invert_wm_value(active->wm[level].plane[plane_id], in vlv_wm_get_hw_state()
6663 vlv_raw_plane_wm_set(crtc_state, level, in vlv_wm_get_hw_state()
6665 vlv_invalidate_wms(crtc, active, level); in vlv_wm_get_hw_state()
6681 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()
6702 int level; in vlv_wm_sanitize() local
6707 for (level = 0; level < wm_state->num_levels; level++) { in vlv_wm_sanitize()
6709 &crtc_state->wm.vlv.raw[level]; in vlv_wm_sanitize()
6713 wm_state->wm[level].plane[plane_id] = in vlv_wm_sanitize()