67 enum mdp5_pipe {  enum
535 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)  in __offset_PIPE()
554 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
556 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
571 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
573 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
575 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
577 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
591 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
605 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
619 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
633 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
641 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
643 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
657 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
659 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return …  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
673 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
675 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
683 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
685 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
693 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
707 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
721 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
735 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
749 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
763 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
765 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
767 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
769 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
771 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
785 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
799 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
801 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
855 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
881 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
898 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
900 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
902 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
904 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
906 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
908 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
910 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
912 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
914 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
916 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
918 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
920 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
943 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { re…  in REG_MDP5_PIPE_SW_PIX_EXT()
945 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_LR()
971 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_TB()
997 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_ty…  in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS()
1011 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
1051 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
1053 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
1055 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
1057 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
1059 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
1061 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()