Lines Matching refs:device
417 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
419 state[__i] = nvkm_rd32(device, NV10_PGRAPH_PIPE_DATA); \
425 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
427 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
433 struct nvkm_device *device = chan->object.engine->subdev.device; in nv17_gr_mthd_lma_window() local
447 PIPE_SAVE(device, pipe_0x0040, 0x0040); in nv17_gr_mthd_lma_window()
448 PIPE_SAVE(device, pipe->pipe_0x0200, 0x0200); in nv17_gr_mthd_lma_window()
450 PIPE_RESTORE(device, chan->lma_window, 0x6790); in nv17_gr_mthd_lma_window()
454 xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); in nv17_gr_mthd_lma_window()
455 xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); in nv17_gr_mthd_lma_window()
457 PIPE_SAVE(device, pipe->pipe_0x4400, 0x4400); in nv17_gr_mthd_lma_window()
458 PIPE_SAVE(device, pipe_0x64c0, 0x64c0); in nv17_gr_mthd_lma_window()
459 PIPE_SAVE(device, pipe_0x6ab0, 0x6ab0); in nv17_gr_mthd_lma_window()
460 PIPE_SAVE(device, pipe_0x6a80, 0x6a80); in nv17_gr_mthd_lma_window()
464 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv17_gr_mthd_lma_window()
465 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv17_gr_mthd_lma_window()
466 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv17_gr_mthd_lma_window()
468 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
470 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
472 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv17_gr_mthd_lma_window()
474 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
476 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); in nv17_gr_mthd_lma_window()
478 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
480 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); in nv17_gr_mthd_lma_window()
481 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); in nv17_gr_mthd_lma_window()
483 PIPE_RESTORE(device, pipe->pipe_0x0200, 0x0200); in nv17_gr_mthd_lma_window()
487 PIPE_RESTORE(device, pipe_0x0040, 0x0040); in nv17_gr_mthd_lma_window()
489 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0); in nv17_gr_mthd_lma_window()
490 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1); in nv17_gr_mthd_lma_window()
492 PIPE_RESTORE(device, pipe_0x64c0, 0x64c0); in nv17_gr_mthd_lma_window()
493 PIPE_RESTORE(device, pipe_0x6ab0, 0x6ab0); in nv17_gr_mthd_lma_window()
494 PIPE_RESTORE(device, pipe_0x6a80, 0x6a80); in nv17_gr_mthd_lma_window()
495 PIPE_RESTORE(device, pipe->pipe_0x4400, 0x4400); in nv17_gr_mthd_lma_window()
497 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); in nv17_gr_mthd_lma_window()
498 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
506 struct nvkm_device *device = chan->object.engine->subdev.device; in nv17_gr_mthd_lma_enable() local
511 nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); in nv17_gr_mthd_lma_enable()
512 nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000); in nv17_gr_mthd_lma_enable()
549 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_channel() local
551 if (nvkm_rd32(device, 0x400144) & 0x00010000) { in nv10_gr_channel()
552 int chid = nvkm_rd32(device, 0x400148) >> 24; in nv10_gr_channel()
564 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_save_pipe() local
583 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_load_pipe() local
589 xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); in nv10_gr_load_pipe()
590 xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); in nv10_gr_load_pipe()
591 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv10_gr_load_pipe()
592 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv10_gr_load_pipe()
593 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv10_gr_load_pipe()
595 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv10_gr_load_pipe()
597 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv10_gr_load_pipe()
599 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv10_gr_load_pipe()
601 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv10_gr_load_pipe()
603 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); in nv10_gr_load_pipe()
605 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv10_gr_load_pipe()
607 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); in nv10_gr_load_pipe()
608 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); in nv10_gr_load_pipe()
615 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0); in nv10_gr_load_pipe()
616 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1); in nv10_gr_load_pipe()
815 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_load_dma_vtxbuf() local
827 int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; in nv10_gr_load_dma_vtxbuf()
839 ctx_user = nvkm_rd32(device, NV10_PGRAPH_CTX_USER); in nv10_gr_load_dma_vtxbuf()
841 ctx_switch[i] = nvkm_rd32(device, NV10_PGRAPH_CTX_SWITCH(i)); in nv10_gr_load_dma_vtxbuf()
844 st2 = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2); in nv10_gr_load_dma_vtxbuf()
845 st2_dl = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DL); in nv10_gr_load_dma_vtxbuf()
846 st2_dh = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DH); in nv10_gr_load_dma_vtxbuf()
847 fifo_ptr = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR); in nv10_gr_load_dma_vtxbuf()
850 fifo[i] = nvkm_rd32(device, 0x4007a0 + 4 * i); in nv10_gr_load_dma_vtxbuf()
854 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), in nv10_gr_load_dma_vtxbuf()
855 nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(subchan, i))); in nv10_gr_load_dma_vtxbuf()
856 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); in nv10_gr_load_dma_vtxbuf()
859 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); in nv10_gr_load_dma_vtxbuf()
860 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, in nv10_gr_load_dma_vtxbuf()
862 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, inst); in nv10_gr_load_dma_vtxbuf()
863 nvkm_mask(device, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); in nv10_gr_load_dma_vtxbuf()
864 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv10_gr_load_dma_vtxbuf()
865 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_load_dma_vtxbuf()
869 nvkm_wr32(device, 0x4007a0 + 4 * i, fifo[i]); in nv10_gr_load_dma_vtxbuf()
871 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); in nv10_gr_load_dma_vtxbuf()
872 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, st2); in nv10_gr_load_dma_vtxbuf()
873 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); in nv10_gr_load_dma_vtxbuf()
874 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); in nv10_gr_load_dma_vtxbuf()
878 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); in nv10_gr_load_dma_vtxbuf()
879 nvkm_wr32(device, NV10_PGRAPH_CTX_USER, ctx_user); in nv10_gr_load_dma_vtxbuf()
886 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_load_context() local
891 nvkm_wr32(device, nv10_gr_ctx_regs[i], chan->nv10[i]); in nv10_gr_load_context()
893 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_load_context()
895 nvkm_wr32(device, nv17_gr_ctx_regs[i], chan->nv17[i]); in nv10_gr_load_context()
900 inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; in nv10_gr_load_context()
903 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); in nv10_gr_load_context()
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); in nv10_gr_load_context()
905 nvkm_mask(device, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); in nv10_gr_load_context()
913 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_unload_context() local
917 chan->nv10[i] = nvkm_rd32(device, nv10_gr_ctx_regs[i]); in nv10_gr_unload_context()
919 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_unload_context()
921 chan->nv17[i] = nvkm_rd32(device, nv17_gr_ctx_regs[i]); in nv10_gr_unload_context()
926 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000000); in nv10_gr_unload_context()
927 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); in nv10_gr_unload_context()
934 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_context_switch() local
947 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; in nv10_gr_context_switch()
958 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_chan_fini() local
962 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv10_gr_chan_fini()
965 nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv10_gr_chan_fini()
1007 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_chan_new() local
1024 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_chan_new()
1027 nvkm_rd32(device, NV10_PGRAPH_DEBUG_4)); in nv10_gr_chan_new()
1028 NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0)); in nv10_gr_chan_new()
1052 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_tile() local
1053 struct nvkm_fifo *fifo = device->fifo; in nv10_gr_tile()
1059 nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); in nv10_gr_tile()
1060 nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); in nv10_gr_tile()
1061 nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr); in nv10_gr_tile()
1085 struct nvkm_device *device = subdev->device; in nv10_gr_intr() local
1086 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); in nv10_gr_intr()
1087 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); in nv10_gr_intr()
1088 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); in nv10_gr_intr()
1089 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); in nv10_gr_intr()
1093 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); in nv10_gr_intr()
1094 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; in nv10_gr_intr()
1111 nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); in nv10_gr_intr()
1117 nvkm_wr32(device, NV03_PGRAPH_INTR, stat); in nv10_gr_intr()
1118 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); in nv10_gr_intr()
1139 struct nvkm_device *device = gr->base.engine.subdev.device; in nv10_gr_init() local
1141 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv10_gr_init()
1142 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv10_gr_init()
1144 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv10_gr_init()
1145 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv10_gr_init()
1146 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700); in nv10_gr_init()
1148 nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); in nv10_gr_init()
1149 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); in nv10_gr_init()
1151 if (device->card_type >= NV_11 && device->chipset >= 0x17) { in nv10_gr_init()
1152 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000); in nv10_gr_init()
1153 nvkm_wr32(device, 0x400a10, 0x03ff3fb6); in nv10_gr_init()
1154 nvkm_wr32(device, 0x400838, 0x002f8684); in nv10_gr_init()
1155 nvkm_wr32(device, 0x40083c, 0x00115f3f); in nv10_gr_init()
1156 nvkm_wr32(device, 0x4006b0, 0x40000020); in nv10_gr_init()
1158 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); in nv10_gr_init()
1161 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); in nv10_gr_init()
1162 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); in nv10_gr_init()
1163 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); in nv10_gr_init()
1164 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); in nv10_gr_init()
1165 nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); in nv10_gr_init()
1166 nvkm_wr32(device, NV10_PGRAPH_STATE, 0xFFFFFFFF); in nv10_gr_init()
1168 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); in nv10_gr_init()
1169 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); in nv10_gr_init()
1170 nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); in nv10_gr_init()
1175 nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, in nv10_gr_new_() argument
1185 return nvkm_gr_ctor(func, device, index, true, &gr->base); in nv10_gr_new_()
1218 nv10_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) in nv10_gr_new() argument
1220 return nv10_gr_new_(&nv10_gr, device, index, pgr); in nv10_gr_new()