Lines Matching refs:state
141 static int write_reg(struct stv *state, u16 reg, u8 val) in write_reg() argument
143 struct i2c_adapter *adap = state->base->i2c; in write_reg()
145 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0, in write_reg()
150 state->base->adr, reg, val); in write_reg()
173 static int read_reg(struct stv *state, u16 reg, u8 *val) in read_reg() argument
175 return i2c_read_regs16(state->base->i2c, state->base->adr, in read_reg()
179 static int read_regs(struct stv *state, u16 reg, u8 *val, int len) in read_regs() argument
181 return i2c_read_regs16(state->base->i2c, state->base->adr, in read_regs()
185 static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) in write_shared_reg() argument
190 mutex_lock(&state->base->reg_lock); in write_shared_reg()
191 status = read_reg(state, reg, &tmp); in write_shared_reg()
193 status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); in write_shared_reg()
194 mutex_unlock(&state->base->reg_lock); in write_shared_reg()
198 static int write_field(struct stv *state, u32 field, u8 val) in write_field() argument
203 status = read_reg(state, field >> 16, &old); in write_field()
211 return write_reg(state, field >> 16, new); in write_field()
215 write_field(state, state->nr ? FSTV0910_P2_##_reg : \
219 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
223 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \
442 static u8 get_optim_cloop(struct stv *state, in get_optim_cloop() argument
452 if (state->symbol_rate <= 3000000) in get_optim_cloop()
454 else if (state->symbol_rate <= 7000000) in get_optim_cloop()
456 else if (state->symbol_rate <= 15000000) in get_optim_cloop()
458 else if (state->symbol_rate <= 25000000) in get_optim_cloop()
469 static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate) in get_cur_symbol_rate() argument
483 if (!state->started) in get_cur_symbol_rate()
486 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); in get_cur_symbol_rate()
487 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); in get_cur_symbol_rate()
488 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); in get_cur_symbol_rate()
489 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); in get_cur_symbol_rate()
490 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); in get_cur_symbol_rate()
491 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); in get_cur_symbol_rate()
492 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0); in get_cur_symbol_rate()
502 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32); in get_cur_symbol_rate()
510 static int get_signal_parameters(struct stv *state) in get_signal_parameters() argument
514 if (!state->started) in get_signal_parameters()
517 if (state->receive_mode == RCVMODE_DVBS2) { in get_signal_parameters()
518 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_signal_parameters()
519 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); in get_signal_parameters()
520 state->pilots = (tmp & 0x01) != 0; in get_signal_parameters()
521 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1); in get_signal_parameters()
523 } else if (state->receive_mode == RCVMODE_DVBS) { in get_signal_parameters()
524 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_signal_parameters()
525 state->puncture_rate = FEC_NONE; in get_signal_parameters()
528 state->puncture_rate = FEC_1_2; in get_signal_parameters()
531 state->puncture_rate = FEC_2_3; in get_signal_parameters()
534 state->puncture_rate = FEC_3_4; in get_signal_parameters()
537 state->puncture_rate = FEC_5_6; in get_signal_parameters()
540 state->puncture_rate = FEC_7_8; in get_signal_parameters()
543 state->is_vcm = 0; in get_signal_parameters()
544 state->is_standard_broadcast = 1; in get_signal_parameters()
545 state->feroll_off = FE_SAT_35; in get_signal_parameters()
550 static int tracking_optimization(struct stv *state) in tracking_optimization() argument
554 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); in tracking_optimization()
557 switch (state->receive_mode) { in tracking_optimization()
568 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
570 if (state->receive_mode == RCVMODE_DVBS2) { in tracking_optimization()
572 write_shared_reg(state, in tracking_optimization()
573 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, in tracking_optimization()
576 if (state->fectype == DVBS2_64K) { in tracking_optimization()
577 u8 aclc = get_optim_cloop(state, state->mod_cod, in tracking_optimization()
578 state->pilots); in tracking_optimization()
580 if (state->mod_cod <= FE_QPSK_910) { in tracking_optimization()
581 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
582 state->regoff, aclc); in tracking_optimization()
583 } else if (state->mod_cod <= FE_8PSK_910) { in tracking_optimization()
584 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
585 state->regoff, 0x2a); in tracking_optimization()
586 write_reg(state, RSTV0910_P2_ACLC2S28 + in tracking_optimization()
587 state->regoff, aclc); in tracking_optimization()
588 } else if (state->mod_cod <= FE_16APSK_910) { in tracking_optimization()
589 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
590 state->regoff, 0x2a); in tracking_optimization()
591 write_reg(state, RSTV0910_P2_ACLC2S216A + in tracking_optimization()
592 state->regoff, aclc); in tracking_optimization()
593 } else if (state->mod_cod <= FE_32APSK_910) { in tracking_optimization()
594 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
595 state->regoff, 0x2a); in tracking_optimization()
596 write_reg(state, RSTV0910_P2_ACLC2S232A + in tracking_optimization()
597 state->regoff, aclc); in tracking_optimization()
640 static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise) in get_signal_to_noise() argument
650 if (!state->started) in get_signal_to_noise()
653 if (state->receive_mode == RCVMODE_DVBS2) { in get_signal_to_noise()
654 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, in get_signal_to_noise()
656 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, in get_signal_to_noise()
661 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, in get_signal_to_noise()
663 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, in get_signal_to_noise()
673 static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator, in get_bit_error_rate_s() argument
678 int status = read_regs(state, in get_bit_error_rate_s()
679 RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s()
686 state->last_berdenominator = 1ULL << ((state->berscale * 2) + in get_bit_error_rate_s()
688 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) | in get_bit_error_rate_s()
690 if (state->last_bernumerator < 256 && state->berscale < 6) { in get_bit_error_rate_s()
691 state->berscale += 1; in get_bit_error_rate_s()
692 status = write_reg(state, RSTV0910_P2_ERRCTRL1 + in get_bit_error_rate_s()
693 state->regoff, in get_bit_error_rate_s()
694 0x20 | state->berscale); in get_bit_error_rate_s()
695 } else if (state->last_bernumerator > 1024 && in get_bit_error_rate_s()
696 state->berscale > 2) { in get_bit_error_rate_s()
697 state->berscale -= 1; in get_bit_error_rate_s()
698 status = write_reg(state, RSTV0910_P2_ERRCTRL1 + in get_bit_error_rate_s()
699 state->regoff, 0x20 | in get_bit_error_rate_s()
700 state->berscale); in get_bit_error_rate_s()
703 *bernumerator = state->last_bernumerator; in get_bit_error_rate_s()
704 *berdenominator = state->last_berdenominator; in get_bit_error_rate_s()
748 static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator, in get_bit_error_rate_s2() argument
753 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s2()
760 state->last_berdenominator = in get_bit_error_rate_s2()
761 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod, in get_bit_error_rate_s2()
762 state->fectype) << in get_bit_error_rate_s2()
763 (state->berscale * 2); in get_bit_error_rate_s2()
764 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) | in get_bit_error_rate_s2()
766 if (state->last_bernumerator < 256 && state->berscale < 6) { in get_bit_error_rate_s2()
767 state->berscale += 1; in get_bit_error_rate_s2()
768 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
769 0x20 | state->berscale); in get_bit_error_rate_s2()
770 } else if (state->last_bernumerator > 1024 && in get_bit_error_rate_s2()
771 state->berscale > 2) { in get_bit_error_rate_s2()
772 state->berscale -= 1; in get_bit_error_rate_s2()
773 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
774 0x20 | state->berscale); in get_bit_error_rate_s2()
777 *bernumerator = state->last_bernumerator; in get_bit_error_rate_s2()
778 *berdenominator = state->last_berdenominator; in get_bit_error_rate_s2()
782 static int get_bit_error_rate(struct stv *state, u32 *bernumerator, in get_bit_error_rate() argument
788 switch (state->receive_mode) { in get_bit_error_rate()
790 return get_bit_error_rate_s(state, in get_bit_error_rate()
793 return get_bit_error_rate_s2(state, in get_bit_error_rate()
801 static int set_mclock(struct stv *state, u32 master_clock) in set_mclock() argument
805 u32 quartz = state->base->extclk / 1000000; in set_mclock()
854 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf); in set_mclock()
855 write_reg(state, RSTV0910_NCOARSE2, odf); in set_mclock()
856 write_reg(state, RSTV0910_NCOARSE1, ndiv); in set_mclock()
859 state->base->mclk = fvco / (2 * odf) * 1000000; in set_mclock()
864 static int stop(struct stv *state) in stop() argument
866 if (state->started) { in stop()
869 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in stop()
870 state->tscfgh | 0x01); in stop()
871 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); in stop()
873 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); in stop()
875 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
877 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
878 state->started = 0; in stop()
880 state->receive_mode = RCVMODE_NONE; in stop()
884 static void set_pls(struct stv *state, u32 pls_code) in set_pls() argument
886 if (pls_code == state->cur_scrambling_code) in set_pls()
890 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, in set_pls()
892 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, in set_pls()
894 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, in set_pls()
896 state->cur_scrambling_code = pls_code; in set_pls()
899 static void set_isi(struct stv *state, u32 isi) in set_isi() argument
908 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, in set_isi()
910 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
916 static void set_stream_modes(struct stv *state, in set_stream_modes() argument
919 set_isi(state, p->stream_id); in set_stream_modes()
920 set_pls(state, p->scrambling_sequence_index); in set_stream_modes()
923 static int init_search_param(struct stv *state, in init_search_param() argument
937 set_stream_modes(state, p); in init_search_param()
941 static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate) in enable_puncture_rate() argument
967 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); in enable_puncture_rate()
970 static int set_vth_default(struct stv *state) in set_vth_default() argument
972 state->vth[0] = 0xd7; in set_vth_default()
973 state->vth[1] = 0x85; in set_vth_default()
974 state->vth[2] = 0x58; in set_vth_default()
975 state->vth[3] = 0x3a; in set_vth_default()
976 state->vth[4] = 0x34; in set_vth_default()
977 state->vth[5] = 0x28; in set_vth_default()
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
983 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
987 static int set_vth(struct stv *state) in set_vth() argument
999 int status = read_regs(state, in set_vth()
1000 RSTV0910_P2_NNOSDATAT1 + state->regoff, in set_vth()
1007 if (state->vth[i] > vth) in set_vth()
1008 state->vth[i] = vth; in set_vth()
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1015 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()
1019 static int start(struct stv *state, struct dtv_frontend_properties *p) in start() argument
1028 state->receive_mode = RCVMODE_NONE; in start()
1029 state->demod_lock_time = 0; in start()
1032 if (state->started) in start()
1033 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1035 init_search_param(state, p); in start()
1038 state->demod_timeout = 3000; in start()
1039 state->fec_timeout = 2000; in start()
1041 state->demod_timeout = 2500; in start()
1042 state->fec_timeout = 1300; in start()
1044 state->demod_timeout = 1000; in start()
1045 state->fec_timeout = 650; in start()
1047 state->demod_timeout = 700; in start()
1048 state->fec_timeout = 350; in start()
1050 state->demod_timeout = 400; in start()
1051 state->fec_timeout = 200; in start()
1053 state->demod_timeout = 300; in start()
1054 state->fec_timeout = 200; in start()
1058 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk); in start()
1059 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, in start()
1061 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1063 state->demod_bits |= 0x80; in start()
1064 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); in start()
1067 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd); in start()
1068 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, in start()
1071 write_shared_reg(state, in start()
1072 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00); in start()
1075 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1076 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1078 enable_puncture_rate(state, FEC_NONE); in start()
1081 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1082 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1083 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1084 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1085 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1086 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1088 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1089 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1090 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1091 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1097 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08); in start()
1098 write_reg(state, RSTV0910_TSTRES0, 0); in start()
1100 set_vth_default(state); in start()
1102 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1104 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1107 freq = (state->search_range / 2000) + 80; in start()
1109 freq = (state->search_range / 2000) + 1600; in start()
1110 freq = (freq << 16) / (state->base->mclk / 1000); in start()
1112 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, in start()
1114 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1117 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, in start()
1119 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1122 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1123 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1125 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1127 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1129 state->demod_lock_time += TUNING_DELAY; in start()
1130 state->started = 1; in start()
1135 static int init_diseqc(struct stv *state) in init_diseqc() argument
1137 u16 offs = state->nr ? 0x40 : 0; /* Address offset */ in init_diseqc()
1138 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32)); in init_diseqc()
1141 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00); in init_diseqc()
1142 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */ in init_diseqc()
1143 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */ in init_diseqc()
1144 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq); in init_diseqc()
1148 static int probe(struct stv *state) in probe() argument
1152 state->receive_mode = RCVMODE_NONE; in probe()
1153 state->started = 0; in probe()
1155 if (read_reg(state, RSTV0910_MID, &id) < 0) in probe()
1162 write_reg(state, RSTV0910_P1_I2CRPT, 0x24); in probe()
1164 write_reg(state, RSTV0910_P2_I2CRPT, 0x24); in probe()
1166 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */ in probe()
1168 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ in probe()
1169 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */ in probe()
1170 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ in probe()
1171 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */ in probe()
1172 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ in probe()
1174 if (state->single) in probe()
1175 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */ in probe()
1177 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ in probe()
1179 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */ in probe()
1180 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */ in probe()
1182 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02); in probe()
1183 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02); in probe()
1184 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04); in probe()
1185 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04); in probe()
1187 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ in probe()
1188 write_reg(state, RSTV0910_TSTRES0, 0x00); in probe()
1190 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00); in probe()
1191 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00); in probe()
1193 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80); in probe()
1194 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80); in probe()
1196 set_mclock(state, 135000000); in probe()
1199 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1200 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); in probe()
1201 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */ in probe()
1202 write_reg(state, RSTV0910_P1_TSCFGL, 0x20); in probe()
1204 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed); in probe()
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1207 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); in probe()
1208 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */ in probe()
1209 write_reg(state, RSTV0910_P2_TSCFGL, 0x20); in probe()
1211 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed); in probe()
1214 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1215 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1216 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); in probe()
1217 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); in probe()
1219 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt); in probe()
1220 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt); in probe()
1222 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17); in probe()
1223 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff); in probe()
1225 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17); in probe()
1226 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff); in probe()
1228 init_diseqc(state); in probe()
1234 struct stv *state = fe->demodulator_priv; in gate_ctrl() local
1235 u8 i2crpt = state->i2crpt & ~0x86; in gate_ctrl()
1248 mutex_lock(&state->base->i2c_lock); in gate_ctrl()
1254 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT : in gate_ctrl()
1257 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) in gate_ctrl()
1258 mutex_unlock(&state->base->i2c_lock); in gate_ctrl()
1259 dev_err(&state->base->i2c->dev, in gate_ctrl()
1265 state->i2crpt = i2crpt; in gate_ctrl()
1268 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock))) in gate_ctrl()
1269 mutex_unlock(&state->base->i2c_lock); in gate_ctrl()
1275 struct stv *state = fe->demodulator_priv; in release() local
1277 state->base->count--; in release()
1278 if (state->base->count == 0) { in release()
1279 list_del(&state->base->stvlist); in release()
1280 kfree(state->base); in release()
1282 kfree(state); in release()
1288 struct stv *state = fe->demodulator_priv; in set_parameters() local
1291 stop(state); in set_parameters()
1294 state->symbol_rate = p->symbol_rate; in set_parameters()
1295 stat = start(state, p); in set_parameters()
1299 static int manage_matype_info(struct stv *state) in manage_matype_info() argument
1301 if (!state->started) in manage_matype_info()
1303 if (state->receive_mode == RCVMODE_DVBS2) { in manage_matype_info()
1306 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, in manage_matype_info()
1308 state->feroll_off = in manage_matype_info()
1310 state->is_vcm = (bbheader[0] & 0x10) == 0; in manage_matype_info()
1311 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0; in manage_matype_info()
1312 } else if (state->receive_mode == RCVMODE_DVBS) { in manage_matype_info()
1313 state->is_vcm = 0; in manage_matype_info()
1314 state->is_standard_broadcast = 1; in manage_matype_info()
1315 state->feroll_off = FE_SAT_35; in manage_matype_info()
1322 struct stv *state = fe->demodulator_priv; in read_snr() local
1326 if (!get_signal_to_noise(state, &snrval)) { in read_snr()
1338 struct stv *state = fe->demodulator_priv; in read_ber() local
1342 get_bit_error_rate(state, &n, &d); in read_ber()
1354 struct stv *state = fe->demodulator_priv; in read_signal_strength() local
1355 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; in read_signal_strength()
1361 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); in read_signal_strength()
1366 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); in read_signal_strength()
1381 struct stv *state = fe->demodulator_priv; in read_status() local
1390 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state); in read_status()
1393 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus); in read_status()
1399 set_vth(state); in read_status()
1415 if (state->receive_mode == RCVMODE_NONE) { in read_status()
1416 state->receive_mode = cur_receive_mode; in read_status()
1417 state->demod_lock_time = jiffies; in read_status()
1418 state->first_time_lock = 1; in read_status()
1420 get_signal_parameters(state); in read_status()
1421 tracking_optimization(state); in read_status()
1423 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1424 state->tscfgh); in read_status()
1426 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1427 state->tscfgh | 0x01); in read_status()
1428 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1429 state->tscfgh); in read_status()
1432 if (state->receive_mode == RCVMODE_DVBS2) { in read_status()
1435 read_reg(state, in read_status()
1436 RSTV0910_P2_PDELSTATUS1 + state->regoff, in read_status()
1442 read_reg(state, in read_status()
1443 RSTV0910_P2_VSTATUSVIT + state->regoff, in read_status()
1452 if (state->first_time_lock) { in read_status()
1455 state->first_time_lock = 0; in read_status()
1457 manage_matype_info(state); in read_status()
1459 if (state->receive_mode == RCVMODE_DVBS2) { in read_status()
1464 state->demod_bits &= ~0x84; in read_status()
1465 write_reg(state, in read_status()
1466 RSTV0910_P2_DEMOD + state->regoff, in read_status()
1467 state->demod_bits); in read_status()
1468 read_reg(state, in read_status()
1469 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1473 write_reg(state, in read_status()
1474 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1478 write_reg(state, in read_status()
1479 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1482 state->berscale = 2; in read_status()
1483 state->last_bernumerator = 0; in read_status()
1484 state->last_berdenominator = 1; in read_status()
1486 write_reg(state, in read_status()
1487 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1488 BER_SRC_S2 | state->berscale); in read_status()
1490 state->berscale = 2; in read_status()
1491 state->last_bernumerator = 0; in read_status()
1492 state->last_berdenominator = 1; in read_status()
1494 write_reg(state, in read_status()
1495 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1496 BER_SRC_S | state->berscale); in read_status()
1499 write_reg(state, in read_status()
1500 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1505 write_reg(state, in read_status()
1506 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1508 set_vth_default(state); in read_status()
1509 if (state->receive_mode == RCVMODE_DVBS) in read_status()
1510 enable_puncture_rate(state, in read_status()
1511 state->puncture_rate); in read_status()
1515 if (state->is_vcm) { in read_status()
1519 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, in read_status()
1523 if (mod_cod > state->mod_cod) in read_status()
1524 state->mod_cod = mod_cod; in read_status()
1553 struct stv *state = fe->demodulator_priv; in get_frontend() local
1557 if (state->receive_mode == RCVMODE_DVBS2) { in get_frontend()
1579 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_frontend()
1584 } else if (state->receive_mode == RCVMODE_DVBS) { in get_frontend()
1585 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_frontend()
1609 if (state->receive_mode != RCVMODE_NONE) { in get_frontend()
1610 get_cur_symbol_rate(state, &symbolrate); in get_frontend()
1620 struct stv *state = fe->demodulator_priv; in tune() local
1627 state->tune_time = jiffies; in tune()
1648 struct stv *state = fe->demodulator_priv; in set_tone() local
1649 u16 offs = state->nr ? 0x40 : 0; in set_tone()
1653 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); in set_tone()
1655 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); in set_tone()
1662 static int wait_dis(struct stv *state, u8 flag, u8 val) in wait_dis() argument
1666 u16 offs = state->nr ? 0x40 : 0; in wait_dis()
1669 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat); in wait_dis()
1680 struct stv *state = fe->demodulator_priv; in send_master_cmd() local
1686 wait_dis(state, 0x40, 0x00); in send_master_cmd()
1690 wait_dis(state, 0x20, 0x20); in send_master_cmd()
1696 struct stv *state = fe->demodulator_priv; in send_burst() local
1708 wait_dis(state, 0x40, 0x00); in send_burst()
1711 wait_dis(state, 0x20, 0x20); in send_burst()
1718 struct stv *state = fe->demodulator_priv; in sleep() local
1720 stop(state); in sleep()
1762 static void stv0910_init_stats(struct stv *state) in stv0910_init_stats() argument
1764 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache; in stv0910_init_stats()
1780 struct stv *state; in stv0910_attach() local
1783 state = kzalloc(sizeof(*state), GFP_KERNEL); in stv0910_attach()
1784 if (!state) in stv0910_attach()
1787 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); in stv0910_attach()
1788 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00; in stv0910_attach()
1789 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); in stv0910_attach()
1791 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28); in stv0910_attach()
1792 state->nr = nr; in stv0910_attach()
1793 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()
1794 state->search_range = 16000000; in stv0910_attach()
1795 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */ in stv0910_attach()
1796 state->receive_mode = RCVMODE_NONE; in stv0910_attach()
1797 state->cur_scrambling_code = (~0U); in stv0910_attach()
1798 state->single = cfg->single ? 1 : 0; in stv0910_attach()
1803 state->base = base; in stv0910_attach()
1815 state->base = base; in stv0910_attach()
1816 if (probe(state) < 0) { in stv0910_attach()
1824 state->fe.ops = stv0910_ops; in stv0910_attach()
1825 state->fe.demodulator_priv = state; in stv0910_attach()
1826 state->nr = nr; in stv0910_attach()
1829 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev)); in stv0910_attach()
1831 stv0910_init_stats(state); in stv0910_attach()
1833 return &state->fe; in stv0910_attach()
1836 kfree(state); in stv0910_attach()