Lines Matching refs:asic
90 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value) in asic3_write_register() argument
92 iowrite16(value, asic->mapping + in asic3_write_register()
93 (reg >> asic->bus_shift)); in asic3_write_register()
97 u32 asic3_read_register(struct asic3 *asic, unsigned int reg) in asic3_read_register() argument
99 return ioread16(asic->mapping + in asic3_read_register()
100 (reg >> asic->bus_shift)); in asic3_read_register()
104 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) in asic3_set_register() argument
109 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_set_register()
110 val = asic3_read_register(asic, reg); in asic3_set_register()
115 asic3_write_register(asic, reg, val); in asic3_set_register()
116 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_set_register()
124 static void asic3_irq_flip_edge(struct asic3 *asic, in asic3_irq_flip_edge() argument
130 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_irq_flip_edge()
131 edge = asic3_read_register(asic, in asic3_irq_flip_edge()
134 asic3_write_register(asic, in asic3_irq_flip_edge()
136 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_flip_edge()
141 struct asic3 *asic = irq_desc_get_handler_data(desc); in asic3_irq_demux() local
152 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
153 status = asic3_read_register(asic, in asic3_irq_demux()
155 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
168 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_irq_demux()
169 istat = asic3_read_register(asic, in asic3_irq_demux()
173 asic3_write_register(asic, in asic3_irq_demux()
176 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_irq_demux()
185 irqnr = asic->irq_base + in asic3_irq_demux()
189 if (asic->irq_bothedge[bank] & bit) in asic3_irq_demux()
190 asic3_irq_flip_edge(asic, base, in asic3_irq_demux()
200 generic_handle_irq(asic->irq_base + i); in asic3_irq_demux()
205 dev_err(asic->dev, "interrupt processing overrun\n"); in asic3_irq_demux()
208 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq) in asic3_irq_to_bank() argument
212 n = (irq - asic->irq_base) >> 4; in asic3_irq_to_bank()
217 static inline int asic3_irq_to_index(struct asic3 *asic, int irq) in asic3_irq_to_index() argument
219 return (irq - asic->irq_base) & 0xf; in asic3_irq_to_index()
224 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_mask_gpio_irq() local
228 bank = asic3_irq_to_bank(asic, data->irq); in asic3_mask_gpio_irq()
229 index = asic3_irq_to_index(asic, data->irq); in asic3_mask_gpio_irq()
231 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_mask_gpio_irq()
232 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_mask_gpio_irq()
234 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); in asic3_mask_gpio_irq()
235 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_gpio_irq()
240 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_mask_irq() local
244 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_mask_irq()
245 regval = asic3_read_register(asic, in asic3_mask_irq()
250 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_mask_irq()
252 asic3_write_register(asic, in asic3_mask_irq()
256 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_mask_irq()
261 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_unmask_gpio_irq() local
265 bank = asic3_irq_to_bank(asic, data->irq); in asic3_unmask_gpio_irq()
266 index = asic3_irq_to_index(asic, data->irq); in asic3_unmask_gpio_irq()
268 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_gpio_irq()
269 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); in asic3_unmask_gpio_irq()
271 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val); in asic3_unmask_gpio_irq()
272 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_gpio_irq()
277 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_unmask_irq() local
281 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_unmask_irq()
282 regval = asic3_read_register(asic, in asic3_unmask_irq()
287 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); in asic3_unmask_irq()
289 asic3_write_register(asic, in asic3_unmask_irq()
293 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_unmask_irq()
298 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_gpio_irq_type() local
303 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_type()
304 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_type()
307 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_irq_type()
308 level = asic3_read_register(asic, in asic3_gpio_irq_type()
310 edge = asic3_read_register(asic, in asic3_gpio_irq_type()
312 trigger = asic3_read_register(asic, in asic3_gpio_irq_type()
314 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; in asic3_gpio_irq_type()
324 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) in asic3_gpio_irq_type()
328 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; in asic3_gpio_irq_type()
341 dev_notice(asic->dev, "irq type not changed\n"); in asic3_gpio_irq_type()
343 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER, in asic3_gpio_irq_type()
345 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER, in asic3_gpio_irq_type()
347 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE, in asic3_gpio_irq_type()
349 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_irq_type()
355 struct asic3 *asic = irq_data_get_irq_chip_data(data); in asic3_gpio_irq_set_wake() local
359 bank = asic3_irq_to_bank(asic, data->irq); in asic3_gpio_irq_set_wake()
360 index = asic3_irq_to_index(asic, data->irq); in asic3_gpio_irq_set_wake()
363 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on); in asic3_gpio_irq_set_wake()
386 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_irq_probe() local
394 asic->irq_nr = ret; in asic3_irq_probe()
398 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_irq_probe()
401 irq_base = asic->irq_base; in asic3_irq_probe()
404 if (irq < asic->irq_base + ASIC3_NUM_GPIOS) in asic3_irq_probe()
409 irq_set_chip_data(irq, asic); in asic3_irq_probe()
414 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK), in asic3_irq_probe()
417 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic); in asic3_irq_probe()
418 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING); in asic3_irq_probe()
425 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_irq_remove() local
428 irq_base = asic->irq_base; in asic3_irq_remove()
435 irq_set_chained_handler(asic->irq_nr, NULL); in asic3_irq_remove()
445 struct asic3 *asic; in asic3_gpio_direction() local
447 asic = gpiochip_get_data(chip); in asic3_gpio_direction()
451 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_direction()
456 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_direction()
458 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION); in asic3_gpio_direction()
466 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg); in asic3_gpio_direction()
468 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_direction()
491 struct asic3 *asic; in asic3_gpio_get() local
493 asic = gpiochip_get_data(chip); in asic3_gpio_get()
497 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_get()
502 return !!(asic3_read_register(asic, in asic3_gpio_get()
512 struct asic3 *asic; in asic3_gpio_set() local
514 asic = gpiochip_get_data(chip); in asic3_gpio_set()
518 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n", in asic3_gpio_set()
525 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_gpio_set()
527 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT); in asic3_gpio_set()
534 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg); in asic3_gpio_set()
536 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_gpio_set()
541 struct asic3 *asic = gpiochip_get_data(chip); in asic3_gpio_to_irq() local
543 return asic->irq_base + offset; in asic3_gpio_to_irq()
549 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_gpio_probe() local
560 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); in asic3_gpio_probe()
561 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); in asic3_gpio_probe()
562 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); in asic3_gpio_probe()
563 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); in asic3_gpio_probe()
583 asic3_write_register(asic, in asic3_gpio_probe()
587 asic3_write_register(asic, in asic3_gpio_probe()
590 asic3_write_register(asic, in asic3_gpio_probe()
596 return gpiochip_add_data(&asic->gpio, asic); in asic3_gpio_probe()
601 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_gpio_remove() local
603 gpiochip_remove(&asic->gpio); in asic3_gpio_remove()
607 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) in asic3_clk_enable() argument
612 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_clk_enable()
614 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_enable()
616 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_enable()
618 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_enable()
621 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk) in asic3_clk_disable() argument
628 raw_spin_lock_irqsave(&asic->lock, flags); in asic3_clk_disable()
630 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX)); in asic3_clk_disable()
632 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex); in asic3_clk_disable()
634 raw_spin_unlock_irqrestore(&asic->lock, flags); in asic3_clk_disable()
658 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_enable() local
661 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_enable()
662 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_enable()
663 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_enable()
667 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), in ds1wm_enable()
670 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET), in ds1wm_enable()
673 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in ds1wm_enable()
682 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in ds1wm_disable() local
684 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in ds1wm_disable()
687 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]); in ds1wm_disable()
688 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in ds1wm_disable()
689 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in ds1wm_disable()
706 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_pwr() local
708 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_pwr()
713 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_clk_div() local
715 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state); in asic3_mmc_clk_div()
740 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_enable() local
743 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
745 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
747 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
749 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
752 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_enable()
756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_enable()
760 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), in asic3_mmc_enable()
763 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_enable()
764 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_enable()
767 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_mmc_enable()
771 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_enable()
775 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift, in asic3_mmc_enable()
783 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_mmc_disable() local
786 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF), in asic3_mmc_disable()
790 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]); in asic3_mmc_disable()
791 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]); in asic3_mmc_disable()
792 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]); in asic3_mmc_disable()
793 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]); in asic3_mmc_disable()
818 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_enable() local
820 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_enable()
828 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_disable() local
830 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_disable()
838 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent); in asic3_leds_suspend() local
840 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0) in asic3_leds_suspend()
843 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]); in asic3_leds_suspend()
879 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_mfd_probe() local
885 dev_dbg(asic->dev, "no SDIO MEM resource\n"); in asic3_mfd_probe()
889 dev_dbg(asic->dev, "no SDIO IRQ resource\n"); in asic3_mfd_probe()
892 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_mfd_probe()
895 ds1wm_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
896 ds1wm_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
900 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> in asic3_mfd_probe()
901 asic->bus_shift) + mem_sdio->start, in asic3_mfd_probe()
902 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift); in asic3_mfd_probe()
903 if (!asic->tmio_cnf) { in asic3_mfd_probe()
905 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n"); in asic3_mfd_probe()
909 asic3_mmc_resources[0].start >>= asic->bus_shift; in asic3_mfd_probe()
910 asic3_mmc_resources[0].end >>= asic->bus_shift; in asic3_mfd_probe()
915 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL); in asic3_mfd_probe()
941 if (asic->tmio_cnf) in asic3_mfd_probe()
942 iounmap(asic->tmio_cnf); in asic3_mfd_probe()
949 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_mfd_remove() local
952 iounmap(asic->tmio_cnf); in asic3_mfd_remove()
959 struct asic3 *asic; in asic3_probe() local
964 asic = devm_kzalloc(&pdev->dev, in asic3_probe()
966 if (!asic) in asic3_probe()
969 raw_spin_lock_init(&asic->lock); in asic3_probe()
970 platform_set_drvdata(pdev, asic); in asic3_probe()
971 asic->dev = &pdev->dev; in asic3_probe()
975 dev_err(asic->dev, "no MEM resource\n"); in asic3_probe()
979 asic->mapping = ioremap(mem->start, resource_size(mem)); in asic3_probe()
980 if (!asic->mapping) { in asic3_probe()
981 dev_err(asic->dev, "Couldn't ioremap\n"); in asic3_probe()
985 asic->irq_base = pdata->irq_base; in asic3_probe()
988 asic->bus_shift = 2 - (resource_size(mem) >> 12); in asic3_probe()
991 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
995 dev_err(asic->dev, "Couldn't probe IRQs\n"); in asic3_probe()
999 asic->gpio.label = "asic3"; in asic3_probe()
1000 asic->gpio.base = pdata->gpio_base; in asic3_probe()
1001 asic->gpio.ngpio = ASIC3_NUM_GPIOS; in asic3_probe()
1002 asic->gpio.get = asic3_gpio_get; in asic3_probe()
1003 asic->gpio.set = asic3_gpio_set; in asic3_probe()
1004 asic->gpio.direction_input = asic3_gpio_direction_input; in asic3_probe()
1005 asic->gpio.direction_output = asic3_gpio_direction_output; in asic3_probe()
1006 asic->gpio.to_irq = asic3_gpio_to_irq; in asic3_probe()
1012 dev_err(asic->dev, "GPIO probe failed\n"); in asic3_probe()
1019 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init)); in asic3_probe()
1023 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_probe()
1026 dev_info(asic->dev, "ASIC3 Core driver\n"); in asic3_probe()
1034 iounmap(asic->mapping); in asic3_probe()
1042 struct asic3 *asic = platform_get_drvdata(pdev); in asic3_remove() local
1044 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), in asic3_remove()
1054 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); in asic3_remove()
1056 iounmap(asic->mapping); in asic3_remove()