Lines Matching refs:ctrl_reg
49 u32 ctrl_reg; in ixgb_mac_reset() local
51 ctrl_reg = IXGB_CTRL0_RST | in ixgb_mac_reset()
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_mac_reset()
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
76 ctrl_reg = /* Enable interrupt from XFP and SerDes */ in ixgb_mac_reset()
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
89 return ctrl_reg; in ixgb_mac_reset()
100 u32 ctrl_reg; in ixgb_adapter_stop() local
137 ctrl_reg = ixgb_mac_reset(hw); in ixgb_adapter_stop()
146 return ctrl_reg & IXGB_CTRL0_RST; in ixgb_adapter_stop()
613 u32 ctrl_reg; in ixgb_setup_fc() local
620 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_setup_fc()
623 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); in ixgb_setup_fc()
637 ctrl_reg |= (IXGB_CTRL0_CMDC); in ixgb_setup_fc()
643 ctrl_reg |= (IXGB_CTRL0_RPE); in ixgb_setup_fc()
649 ctrl_reg |= (IXGB_CTRL0_TPE); in ixgb_setup_fc()
656 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); in ixgb_setup_fc()
667 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_setup_fc()