Lines Matching refs:SMC_REG

489 #define TCR_REG(lp) 	SMC_REG(lp, 0x0000, 0)
508 #define EPH_STATUS_REG(lp)	SMC_REG(lp, 0x0002, 0)
527 #define RCR_REG(lp)		SMC_REG(lp, 0x0004, 0)
544 #define COUNTER_REG(lp)	SMC_REG(lp, 0x0006, 0)
549 #define MIR_REG(lp)		SMC_REG(lp, 0x0008, 0)
554 #define RPC_REG(lp)		SMC_REG(lp, 0x000A, 0)
580 #define CONFIG_REG(lp)	SMC_REG(lp, 0x0000,	1)
592 #define BASE_REG(lp)	SMC_REG(lp, 0x0002, 1)
597 #define ADDR0_REG(lp)	SMC_REG(lp, 0x0004, 1)
598 #define ADDR1_REG(lp)	SMC_REG(lp, 0x0006, 1)
599 #define ADDR2_REG(lp)	SMC_REG(lp, 0x0008, 1)
604 #define GP_REG(lp)		SMC_REG(lp, 0x000A, 1)
609 #define CTL_REG(lp)		SMC_REG(lp, 0x000C, 1)
622 #define MMU_CMD_REG(lp)	SMC_REG(lp, 0x0000, 2)
636 #define PN_REG(lp)		SMC_REG(lp, 0x0002, 2)
641 #define AR_REG(lp)		SMC_REG(lp, 0x0003, 2)
647 #define TXFIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)
652 #define RXFIFO_REG(lp)	SMC_REG(lp, 0x0005, 2)
655 #define FIFO_REG(lp)	SMC_REG(lp, 0x0004, 2)
659 #define PTR_REG(lp)		SMC_REG(lp, 0x0006, 2)
667 #define DATA_REG(lp)	SMC_REG(lp, 0x0008, 2)
672 #define INT_REG(lp)		SMC_REG(lp, 0x000C, 2)
677 #define IM_REG(lp)		SMC_REG(lp, 0x000D, 2)
690 #define MCAST_REG1(lp)	SMC_REG(lp, 0x0000, 3)
691 #define MCAST_REG2(lp)	SMC_REG(lp, 0x0002, 3)
692 #define MCAST_REG3(lp)	SMC_REG(lp, 0x0004, 3)
693 #define MCAST_REG4(lp)	SMC_REG(lp, 0x0006, 3)
698 #define MII_REG(lp)		SMC_REG(lp, 0x0008, 3)
709 #define REV_REG(lp)		SMC_REG(lp, 0x000A, 3)
715 #define ERCV_REG(lp)	SMC_REG(lp, 0x000C, 3)
722 #define EXT_REG(lp)		SMC_REG(lp, 0x0000, 7)
846 #define SMC_REG(lp, reg, bank)					\  macro
857 #define SMC_REG(lp, reg, bank)	(reg<<SMC_IO_SHIFT)  macro
878 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));	\
958 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));	\
980 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));	\
998 			SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));	\