Lines Matching refs:bank
23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
78 bank = 0; in vsc8584_macsec_phy_write()
85 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_write()
97 enum macsec_bank bank) in vsc8584_macsec_classification() argument
100 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_CP_TAG, in vsc8584_macsec_classification()
107 enum macsec_bank bank, in vsc8584_macsec_flow_default_action() argument
110 u32 port = (bank == MACSEC_INGR) ? in vsc8584_macsec_flow_default_action()
117 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_NCP, in vsc8584_macsec_flow_default_action()
134 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_NM_FLOW_CP, in vsc8584_macsec_flow_default_action()
154 enum macsec_bank bank) in vsc8584_macsec_integrity_checks() argument
158 if (bank != MACSEC_INGR) in vsc8584_macsec_integrity_checks()
162 val = vsc8584_macsec_phy_read(phydev, bank, in vsc8584_macsec_integrity_checks()
166 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CC_CONTROL, in vsc8584_macsec_integrity_checks()
169 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PARAMS2_IG_CP_TAG, in vsc8584_macsec_integrity_checks()
176 enum macsec_bank bank) in vsc8584_macsec_block_init() argument
181 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, in vsc8584_macsec_block_init()
186 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, in vsc8584_macsec_block_init()
189 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_STATUS_CONTEXT_CTRL, in vsc8584_macsec_block_init()
190 bank == MACSEC_INGR ? 0xe5880214 : 0xe5880218); in vsc8584_macsec_block_init()
191 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_MISC_CONTROL, in vsc8584_macsec_block_init()
192 MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(bank == MACSEC_INGR ? 57 : 40) | in vsc8584_macsec_block_init()
193 MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(bank == MACSEC_INGR ? 1 : 2)); in vsc8584_macsec_block_init()
196 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL); in vsc8584_macsec_block_init()
198 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val); in vsc8584_macsec_block_init()
201 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_PP_CTRL, in vsc8584_macsec_block_init()
204 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_BLOCK_CTX_UPDATE, 0x3); in vsc8584_macsec_block_init()
206 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_COUNT_CONTROL); in vsc8584_macsec_block_init()
208 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_COUNT_CONTROL, val); in vsc8584_macsec_block_init()
211 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_NON_VLAN_MTU_CHECK, in vsc8584_macsec_block_init()
216 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_VLAN_MTU_CHECK(i), in vsc8584_macsec_block_init()
220 if (bank == MACSEC_EGR) { in vsc8584_macsec_block_init()
221 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_INTR_CTRL_STATUS); in vsc8584_macsec_block_init()
223 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_INTR_CTRL_STATUS, val); in vsc8584_macsec_block_init()
225 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_FC_CFG, in vsc8584_macsec_block_init()
233 vsc8584_macsec_classification(phydev, bank); in vsc8584_macsec_block_init()
234 vsc8584_macsec_flow_default_action(phydev, bank, false); in vsc8584_macsec_block_init()
235 vsc8584_macsec_integrity_checks(phydev, bank); in vsc8584_macsec_block_init()
238 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_ENA_CFG, in vsc8584_macsec_block_init()
245 enum macsec_bank bank) in vsc8584_macsec_mac_init() argument
252 vsc8584_macsec_phy_write(phydev, bank, 0x1c + i, 0); in vsc8584_macsec_mac_init()
254 val = vsc8584_macsec_phy_read(phydev, bank, in vsc8584_macsec_mac_init()
259 vsc8584_macsec_phy_write(phydev, bank, in vsc8584_macsec_mac_init()
262 val = vsc8584_macsec_phy_read(phydev, bank, in vsc8584_macsec_mac_init()
265 vsc8584_macsec_phy_write(phydev, bank, in vsc8584_macsec_mac_init()
268 val = vsc8584_macsec_phy_read(phydev, bank, in vsc8584_macsec_mac_init()
270 if (bank == HOST_MAC) in vsc8584_macsec_mac_init()
278 vsc8584_macsec_phy_write(phydev, bank, in vsc8584_macsec_mac_init()
281 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_PKTINF_CFG, in vsc8584_macsec_mac_init()
287 (bank == HOST_MAC ? in vsc8584_macsec_mac_init()
292 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MODE_CFG); in vsc8584_macsec_mac_init()
294 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MODE_CFG, val); in vsc8584_macsec_mac_init()
296 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG); in vsc8584_macsec_mac_init()
299 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_MAXLEN_CFG, val); in vsc8584_macsec_mac_init()
301 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ADV_CHK_CFG, in vsc8584_macsec_mac_init()
307 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MAC_CFG_LFS_CFG); in vsc8584_macsec_mac_init()
309 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_LFS_CFG, val); in vsc8584_macsec_mac_init()
311 vsc8584_macsec_phy_write(phydev, bank, MSCC_MAC_CFG_ENA_CFG, in vsc8584_macsec_mac_init()
374 enum macsec_bank bank = flow->bank; in vsc8584_macsec_flow() local
382 if (bank == MACSEC_INGR && flow->assoc_num >= 0) { in vsc8584_macsec_flow()
387 if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) { in vsc8584_macsec_flow()
394 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx), in vsc8584_macsec_flow()
396 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx), in vsc8584_macsec_flow()
403 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx), in vsc8584_macsec_flow()
409 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MISC_MATCH(idx), match); in vsc8584_macsec_flow()
410 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MASK(idx), mask); in vsc8584_macsec_flow()
418 action = (bank == MACSEC_INGR) ? in vsc8584_macsec_flow()
428 if (bank == MACSEC_INGR) { in vsc8584_macsec_flow()
435 } else if (bank == MACSEC_EGR) { in vsc8584_macsec_flow()
445 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val); in vsc8584_macsec_flow()
449 enum macsec_bank bank) in vsc8584_macsec_find_flow() argument
455 if (pos->assoc_num == ctx->sa.assoc_num && pos->bank == bank) in vsc8584_macsec_find_flow()
464 enum macsec_bank bank = flow->bank; in vsc8584_macsec_flow_enable() local
467 if ((flow->bank == MACSEC_INGR && flow->rx_sa && !flow->rx_sa->active) || in vsc8584_macsec_flow_enable()
468 (flow->bank == MACSEC_EGR && flow->tx_sa && !flow->tx_sa->active)) in vsc8584_macsec_flow_enable()
472 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_SET1, BIT(idx)); in vsc8584_macsec_flow_enable()
475 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx)); in vsc8584_macsec_flow_enable()
477 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val); in vsc8584_macsec_flow_enable()
483 enum macsec_bank bank = flow->bank; in vsc8584_macsec_flow_disable() local
487 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_ENTRY_CLEAR1, BIT(idx)); in vsc8584_macsec_flow_disable()
490 val = vsc8584_macsec_phy_read(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx)); in vsc8584_macsec_flow_disable()
492 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_FLOW_CTRL(idx), val); in vsc8584_macsec_flow_disable()
497 if (flow->bank == MACSEC_INGR) in vsc8584_macsec_flow_context_id()
524 enum macsec_bank bank = flow->bank; in vsc8584_macsec_transformation() local
545 control |= (bank == MACSEC_EGR) ? in vsc8584_macsec_transformation()
555 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), in vsc8584_macsec_transformation()
559 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), in vsc8584_macsec_transformation()
564 vsc8584_macsec_phy_write(phydev, bank, in vsc8584_macsec_transformation()
570 vsc8584_macsec_phy_write(phydev, bank, in vsc8584_macsec_transformation()
575 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), in vsc8584_macsec_transformation()
576 bank == MACSEC_INGR ? in vsc8584_macsec_transformation()
579 if (bank == MACSEC_INGR) in vsc8584_macsec_transformation()
581 vsc8584_macsec_phy_write(phydev, bank, in vsc8584_macsec_transformation()
586 sci = (__force u64)(bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci); in vsc8584_macsec_transformation()
587 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), in vsc8584_macsec_transformation()
589 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), in vsc8584_macsec_transformation()
593 vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++), in vsc8584_macsec_transformation()
601 enum macsec_bank bank) in vsc8584_macsec_alloc_flow() argument
603 unsigned long *bitmap = bank == MACSEC_INGR ? in vsc8584_macsec_alloc_flow()
619 flow->bank = bank; in vsc8584_macsec_alloc_flow()
630 unsigned long *bitmap = flow->bank == MACSEC_INGR ? in vsc8584_macsec_free_flow()
856 if (flow->bank == MACSEC_INGR && flow->rx_sa && in vsc8584_macsec_del_rxsc()
1015 if (flow->bank != MACSEC_EGR || !flow->has_transformation) in vsc8584_handle_macsec_interrupt()