30 #define GPIO_BANK_START(bank)		((bank) * PINS_PER_BANK)  argument
71 	unsigned int bank;  member
275 		.bank = _pin / PINS_PER_BANK,				\
601 				fname, pg->bank, pg->pin,  in oxnas_ox810se_pinmux_enable()
605 					  (pg->bank ?  in oxnas_ox810se_pinmux_enable()
612 					  (pg->bank ?  in oxnas_ox810se_pinmux_enable()
619 					  (pg->bank ?  in oxnas_ox810se_pinmux_enable()
645 	unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);  in oxnas_ox820_pinmux_enable()
652 				fname, pg->bank, pg->pin,  in oxnas_ox820_pinmux_enable()
697 	struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);  in oxnas_ox810se_gpio_request_enable()  local
698 	u32 mask = BIT(offset - bank->gpio_chip.base);  in oxnas_ox810se_gpio_request_enable()
701 		offset, bank->gpio_chip.base, bank->id, mask);  in oxnas_ox810se_gpio_request_enable()
704 			  (bank->id ?  in oxnas_ox810se_gpio_request_enable()
709 			  (bank->id ?  in oxnas_ox810se_gpio_request_enable()
714 			  (bank->id ?  in oxnas_ox810se_gpio_request_enable()
727 	struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);  in oxnas_ox820_gpio_request_enable()  local
728 	unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);  in oxnas_ox820_gpio_request_enable()
729 	u32 mask = BIT(offset - bank->gpio_chip.base);  in oxnas_ox820_gpio_request_enable()
732 		offset, bank->gpio_chip.base, bank->id, mask);  in oxnas_ox820_gpio_request_enable()
756 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_get_direction()  local
759 	if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)  in oxnas_gpio_get_direction()
768 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_direction_input()  local
771 	writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);  in oxnas_gpio_direction_input()
778 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_get()  local
781 	return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;  in oxnas_gpio_get()
787 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_set()  local
791 		writel_relaxed(mask, bank->reg_base + OUTPUT_SET);  in oxnas_gpio_set()
793 		writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);  in oxnas_gpio_set()
799 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_direction_output()  local
803 	writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);  in oxnas_gpio_direction_output()
844 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);  in oxnas_ox810se_pinconf_get()  local
846 	u32 mask = BIT(pin - bank->gpio_chip.base);  in oxnas_ox810se_pinconf_get()
853 				  (bank->id ?  in oxnas_ox810se_pinconf_get()
875 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);  in oxnas_ox820_pinconf_get()  local
877 	unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);  in oxnas_ox820_pinconf_get()
878 	u32 mask = BIT(pin - bank->gpio_chip.base);  in oxnas_ox820_pinconf_get()
906 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);  in oxnas_ox810se_pinconf_set()  local
909 	u32 offset = pin - bank->gpio_chip.base;  in oxnas_ox810se_pinconf_set()
913 		pin, bank->gpio_chip.base, mask);  in oxnas_ox810se_pinconf_set()
922 					  (bank->id ?  in oxnas_ox810se_pinconf_set()
942 	struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);  in oxnas_ox820_pinconf_set()  local
943 	unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);  in oxnas_ox820_pinconf_set()
946 	u32 offset = pin - bank->gpio_chip.base;  in oxnas_ox820_pinconf_set()
950 		pin, bank->gpio_chip.base, mask);  in oxnas_ox820_pinconf_set()
987 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_irq_ack()  local
990 	writel(mask, bank->reg_base + IRQ_PENDING);  in oxnas_gpio_irq_ack()
996 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_irq_mask()  local
1001 		writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,  in oxnas_gpio_irq_mask()
1002 		       bank->reg_base + RE_IRQ_ENABLE);  in oxnas_gpio_irq_mask()
1005 		writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,  in oxnas_gpio_irq_mask()
1006 		       bank->reg_base + FE_IRQ_ENABLE);  in oxnas_gpio_irq_mask()
1012 	struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);  in oxnas_gpio_irq_unmask()  local
1017 		writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,  in oxnas_gpio_irq_unmask()
1018 		       bank->reg_base + RE_IRQ_ENABLE);  in oxnas_gpio_irq_unmask()
1021 		writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,  in oxnas_gpio_irq_unmask()
1022 		       bank->reg_base + FE_IRQ_ENABLE);  in oxnas_gpio_irq_unmask()
1048 	struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);  in oxnas_gpio_irq_handler()  local
1055 	stat = readl(bank->reg_base + IRQ_PENDING);  in oxnas_gpio_irq_handler()
1199 	struct oxnas_gpio_bank *bank;  in oxnas_gpio_probe()  local
1223 	bank = &oxnas_gpio_banks[id];  in oxnas_gpio_probe()
1225 	bank->reg_base = devm_platform_ioremap_resource(pdev, 0);  in oxnas_gpio_probe()
1226 	if (IS_ERR(bank->reg_base))  in oxnas_gpio_probe()
1227 		return PTR_ERR(bank->reg_base);  in oxnas_gpio_probe()
1233 	bank->id = id;  in oxnas_gpio_probe()
1234 	bank->gpio_chip.parent = &pdev->dev;  in oxnas_gpio_probe()
1235 	bank->gpio_chip.of_node = np;  in oxnas_gpio_probe()
1236 	bank->gpio_chip.ngpio = ngpios;  in oxnas_gpio_probe()
1237 	girq = &bank->gpio_chip.irq;  in oxnas_gpio_probe()
1238 	girq->chip = &bank->irq_chip;  in oxnas_gpio_probe()
1249 	ret = gpiochip_add_data(&bank->gpio_chip, bank);  in oxnas_gpio_probe()