Lines Matching refs:bank
153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_bias() argument
186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
195 stm32_gpio_backup_value(bank, offset, value); in __stm32_gpio_set()
200 clk_enable(bank->clk); in __stm32_gpio_set()
202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
204 clk_disable(bank->clk); in __stm32_gpio_set()
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_noclk() local
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get_noclk()
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
240 clk_enable(bank->clk); in stm32_gpio_get()
244 clk_disable(bank->clk); in stm32_gpio_get()
251 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_set() local
253 __stm32_gpio_set(bank, offset, value); in stm32_gpio_set()
264 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_direction_output() local
266 __stm32_gpio_set(bank, offset, value); in stm32_gpio_direction_output()
275 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_to_irq() local
278 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
288 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_direction() local
293 stm32_pmx_get_mode(bank, pin, &mode, &alt); in stm32_gpio_get_direction()
318 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger() local
322 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
326 level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
327 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
328 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
340 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type() local
359 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
366 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources() local
367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
371 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
375 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
384 clk_enable(bank->clk); in stm32_gpio_irq_request_resources()
391 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources() local
393 if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK) in stm32_gpio_irq_release_resources()
394 clk_disable(bank->clk); in stm32_gpio_irq_release_resources()
396 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
434 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate() local
435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
465 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
478 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_deactivate() local
479 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_deactivate()
491 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc() local
503 bank); in stm32_gpio_domain_alloc()
763 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, in stm32_pmx_set_mode() argument
766 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode()
773 clk_enable(bank->clk); in stm32_pmx_set_mode()
774 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
785 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
788 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
790 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
793 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
798 stm32_gpio_backup_mode(bank, pin, mode, alt); in stm32_pmx_set_mode()
801 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
802 clk_disable(bank->clk); in stm32_pmx_set_mode()
807 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, in stm32_pmx_get_mode() argument
815 clk_enable(bank->clk); in stm32_pmx_get_mode()
816 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
818 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
822 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
826 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
827 clk_disable(bank->clk); in stm32_pmx_get_mode()
838 struct stm32_gpio_bank *bank; in stm32_pmx_set_mux() local
855 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
861 return stm32_pmx_set_mode(bank, pin, mode, alt); in stm32_pmx_set_mux()
868 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction() local
871 return stm32_pmx_set_mode(bank, pin, !input, 0); in stm32_pmx_gpio_set_direction()
885 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, in stm32_pconf_set_driving() argument
888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving()
893 clk_enable(bank->clk); in stm32_pconf_set_driving()
894 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
905 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
908 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
913 stm32_gpio_backup_driving(bank, offset, drive); in stm32_pconf_set_driving()
916 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
917 clk_disable(bank->clk); in stm32_pconf_set_driving()
922 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, in stm32_pconf_get_driving() argument
928 clk_enable(bank->clk); in stm32_pconf_get_driving()
929 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
931 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
934 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
935 clk_disable(bank->clk); in stm32_pconf_get_driving()
940 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, in stm32_pconf_set_speed() argument
943 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed()
948 clk_enable(bank->clk); in stm32_pconf_set_speed()
949 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
968 stm32_gpio_backup_speed(bank, offset, speed); in stm32_pconf_set_speed()
971 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
972 clk_disable(bank->clk); in stm32_pconf_set_speed()
977 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, in stm32_pconf_get_speed() argument
983 clk_enable(bank->clk); in stm32_pconf_get_speed()
984 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
986 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
989 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
990 clk_disable(bank->clk); in stm32_pconf_get_speed()
995 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, in stm32_pconf_set_bias() argument
998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias()
1003 clk_enable(bank->clk); in stm32_pconf_set_bias()
1004 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1015 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1018 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1023 stm32_gpio_backup_bias(bank, offset, bias); in stm32_pconf_set_bias()
1026 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1027 clk_disable(bank->clk); in stm32_pconf_set_bias()
1032 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, in stm32_pconf_get_bias() argument
1038 clk_enable(bank->clk); in stm32_pconf_get_bias()
1039 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1041 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1044 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1045 clk_disable(bank->clk); in stm32_pconf_get_bias()
1050 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, in stm32_pconf_get() argument
1056 clk_enable(bank->clk); in stm32_pconf_get()
1057 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1060 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1063 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1066 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1067 clk_disable(bank->clk); in stm32_pconf_get()
1078 struct stm32_gpio_bank *bank; in stm32_pconf_parse_conf() local
1087 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1092 ret = stm32_pconf_set_driving(bank, offset, 0); in stm32_pconf_parse_conf()
1095 ret = stm32_pconf_set_driving(bank, offset, 1); in stm32_pconf_parse_conf()
1098 ret = stm32_pconf_set_speed(bank, offset, arg); in stm32_pconf_parse_conf()
1101 ret = stm32_pconf_set_bias(bank, offset, 0); in stm32_pconf_parse_conf()
1104 ret = stm32_pconf_set_bias(bank, offset, 1); in stm32_pconf_parse_conf()
1107 ret = stm32_pconf_set_bias(bank, offset, 2); in stm32_pconf_parse_conf()
1110 __stm32_gpio_set(bank, offset, arg); in stm32_pconf_parse_conf()
1174 struct stm32_gpio_bank *bank; in stm32_pconf_dbg_show() local
1189 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1192 stm32_pmx_get_mode(bank, offset, &mode, &alt); in stm32_pconf_dbg_show()
1193 bias = stm32_pconf_get_bias(bank, offset); in stm32_pconf_dbg_show()
1200 val = stm32_pconf_get(bank, offset, true); in stm32_pconf_dbg_show()
1208 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1209 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1210 val = stm32_pconf_get(bank, offset, false); in stm32_pconf_dbg_show()
1220 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1221 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1244 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank() local
1246 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1253 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1254 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1259 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1260 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1261 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1263 err = clk_prepare(bank->clk); in stm32_gpiolib_register_bank()
1269 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1271 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1275 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1283 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1284 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1289 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1297 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1299 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1300 bank->gpio_chip.of_node = np; in stm32_gpiolib_register_bank()
1301 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1302 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1303 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1304 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1308 bank->fwnode = of_node_to_fwnode(np); in stm32_gpiolib_register_bank()
1310 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1311 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1312 bank); in stm32_gpiolib_register_bank()
1314 if (!bank->domain) in stm32_gpiolib_register_bank()
1318 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1324 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1569 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe() local
1572 bank->rstc = of_reset_control_get_exclusive(child, in stm32_pctl_probe()
1574 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) in stm32_pctl_probe()
1577 bank->clk = of_clk_get_by_name(child, NULL); in stm32_pctl_probe()
1578 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1579 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) in stm32_pctl_probe()
1582 PTR_ERR(bank->clk)); in stm32_pctl_probe()
1583 return PTR_ERR(bank->clk); in stm32_pctl_probe()
1612 struct stm32_gpio_bank *bank; in stm32_pinctrl_restore_gpio_regs() local
1625 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1627 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1629 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1632 ret = stm32_pmx_set_mode(bank, offset, mode, alt); in stm32_pinctrl_restore_gpio_regs()
1637 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1639 __stm32_gpio_set(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1642 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1644 ret = stm32_pconf_set_driving(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1648 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1650 ret = stm32_pconf_set_speed(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1654 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1656 ret = stm32_pconf_set_bias(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1661 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()